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The Blue Genet/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is the simultaneous instantiation of multiple PowerPCt cores, highperformance static random access memory (SRAM), DRAM, and several other logic design blocks on a single-platform technology. The IBM embedded DRAM platform allows this seamless integration without compromising performance, reliability, or yield. We discuss the process architecture, the key parameters of the logic components used in the processor cores and other logic design blocks, the SRAM features used in the L2 cache, and the embedded DRAM that forms the L3 cache. We also discuss the evolution of embedded DRAM technology into a higherperformance space in the 90-nm and 65-nm nodes and the potential for dynamic memory to improve overall memory subsystem performance.

A high performance embedded DRAM with deep trench capacitor and high performance SOI logic has been deployed in 45nm and 32nm technology nodes. Following a yield ramp of the sub-2ns latency 45nm technology, we present, for the first time, a 32nm eDRAM technology fully compatible with high performance logic with high-κ metal gate access transistor and high-κ node dielectric for the deep trench storage capacitor.We also describe the technology advancements required to scale the deep trench as well as the access transistor for optimal cell retention and performance. A clear scaling path is seen for the 22nm technology node.

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We present a 65nm embedded DRAM cell (0.127 µm 2 cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL) (1). The cell utilizes a low-leakage 2.2-nm gate oxide pass transistor and a deep trench capacitor. A trench side wall spacer process enables a simplified collarless process. Connection to the buried plate is realized by silicided substrate guardrings with fully landed tungsten contacts. The bitline structure and the deep trench capacitor are designed for high transfer ratio and low RC constant which ensure high performance and sufficient sensing signal. The pass transistor is strain engineered to boost on current and employs optimized S/D junctions to help attain sub-pA off current. This technology has produced fully-functional 2Mb prototype embedded macros with sub-1.5ns latency and sub-2ns random cycle times for on-processor caches. The low leakage device developed also enables for the first time a low standby power SOI technology.

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