Embedded DRAM: Technology platform for the Blue Gene/L chip

Iyer, Subramanian S.; Barth, J.; Parries, P.; Norum, J.; Rice, J.; Logan, L. R.; Hoyniak, D.

doi:10.1147/rd.492.0333

Cited by 65 publications

(23 citation statements)

References 24 publications

(24 reference statements)

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“…A Blue Gene/P node consists of the quad-core Blue Gene/P Compute Chip (BPC) and forty DDR3 DRAM chips, all soldered onto a printed circuit board for reliability. The BPC ASIC also includes a large L3 cache built from embedded DRAM [14], a 3D torus interconnect for MPI point-to-point operations, a tree network for MPI collectives, and a barrier network. A node card (NC) contains 32 compute nodes and up to two I/O nodes (IONs).…”

Section: Blue Gene/p Architecture and Power Flowmentioning

confidence: 99%

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Measuring power consumption on IBM Blue Gene/P

Hennecke¹,

Frings

Homberg

et al. 2011

Comput Sci Res Dev

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Energy efficiency is a key design principle of the IBM Blue Gene series of supercomputers, and Blue Gene systems have consistently gained top GFlops/Watt rankings on the Green500 list. The Blue Gene hardware and management software provide built-in features to monitor power consumption at all levels of the machine's power distribution network. This paper presents the Blue Gene/P power measurement infrastructure and discusses the operational aspects of using this infrastructure on Petascale machines. We also describe the integration of Blue Gene power monitoring capabilities into system-level tools like LLview, and highlight some results of analyzing the production workload at Research Center Jülich (FZJ).

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Section: Blue Gene/p Architecture and Power Flowmentioning

confidence: 99%

“…Those two voltage domains indicate core power (1.2 V) and memory power (1.8 V). The L3 cache on the BPC ASICs, which is implemented as eDRAM [14], is also powered at 1.8 V and included in the memory power.…”

Section: Blue Gene/p Power Consumption Detailsmentioning

confidence: 99%

Measuring power consumption on IBM Blue Gene/P

Hennecke¹,

Frings

Homberg

et al. 2011

Comput Sci Res Dev

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“…This requires additional circuitry making DRAM a poor choice for simple systems such as smaller embedded processors. However, as embedded processors are becoming more complex, on-chip DRAM memories are beginning to be used [4,7]. The rewriting and refreshing also slows down the rates that DRAM can operate.…”

Section: Contributions Of Robert Dennardmentioning

confidence: 99%

The 2007 Benjamin Franklin medal in electrical engineering presented to Robert H. Dennard, Ph.D.

Dobbins¹,

Kapps

2011

Journal of the Franklin Institute

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“…Perhaps the most compelling advantage of this capability is that it allows a massive communication bandwidth to be achieved between the processor cores and memory. In typical 2D chips, the fast cache memory is composed of static RAM (SRAM) or embedded DRAM (eDRAM) [4] that is integrated directly onto the chip. Such schemes work well for single-threaded or fewthreaded architectures.…”

Section: Motivation For 3d Integrationmentioning

confidence: 99%

Wafer-level 3D integration technology

et al. 2008

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An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed. IntroductionThe last few decades have seen an astonishing increase in the functionality of computational systems. This capability has been driven by the scaling of semiconductor devices, which has enabled the number of transistors on a single chip to grow at a geometric rate, following Moore's Law [1]. In particular, the scaling of silicon metal-oxide semiconductor field-effect transistors (MOSFETs) [2] drives the effort to continue this trend into the future.However, several serious roadblocks exist. The first is the difficulty and expense of continued lithographic scaling, which could make it economically impractical to scale devices beyond a certain pitch. The second is that even if lithographic scaling can continue, the power dissipated by the transistors will bring clock frequency scaling to a halt. In fact, it could be argued that clock frequency scaling has already stopped, and microprocessor designs have increasingly relied on new architectures to improve performance. These factors suggest that in the near future, it will no longer be possible to improve system performance through scaling alone, and that additional methods to achieve the desired enhancement will be needed. Three-dimensional (3D) integration technology offers the promise of being a new way of increasing system performance, even in the absence of scaling. This promise is due to a number of characteristic features of 3D integration, including decreased total wiring length (and thus reduced interconnect delay times), a dramatically increased number of interconnects between chips, and the ability to allow dissimilar materials, process technologies, and functions to be integrated. Motivation for 3D integration

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Embedded DRAM: Technology platform for the Blue Gene/L chip

Cited by 65 publications

References 24 publications

Measuring power consumption on IBM Blue Gene/P

Measuring power consumption on IBM Blue Gene/P

The 2007 Benjamin Franklin medal in electrical engineering presented to Robert H. Dennard, Ph.D.

Wafer-level 3D integration technology

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