An 800-MHz embedded DRAM with a concurrent refresh mode

Kirihata, T.; Parries, P.; Hanson, David R.; Kim, Hoki; Golz, John; Fredeman, Gregory; Rajeevakumar, R.; Griesemer, J.; Robson, N.; Cestero, Alberto; Khan, Babar A.; Geng, Wang; Wordeman, M.R.; Iyer, Subramanian S.

doi:10.1109/jssc.2005.848019

Cited by 36 publications

(14 citation statements)

References 16 publications

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“…Thus, the cell area is not affected by the capacitance value [15]. Indeed, as shown in [16], the capacitance values analyzed in this work can be obtained with trench capacitors. Table III shows the area (in m ) of the conventional SRAM and eDRAM cells and the macrocell varying the number of data bits from 1-to 4-bit.…”

Section: Areamentioning

confidence: 85%

Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches

Valero

Sahuquillo

Lorente

et al. 2012

IEEE Trans. VLSI Syst.

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Valero Bresó, A.; Sahuquillo Borrás, J.; Lorente Garcés, VJ.; Petit Martí, SV.; López Rodríguez, PJ.; Duato Marín, JF. (2012). Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20(6):1108-1117. doi:10.1109/TVLSI.2011 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. Abstract-Cache memories dissipate an important amount of the energy budget in current microprocessors. This is mainly due to cache cells are typically implemented with six transistors. To tackle this design concern, recent research has focused on the proposal of new cache cells. An -bit cache cell, namely macrocell, has been proposed in a previous work. This cell combines SRAM and eDRAM technologies with the aim of reducing energy consumption while maintaining the performance. The capacitance of eDRAM cells impacts on energy consumption and performance since these cells lose their state once the retention time expires. On such a case, data must be fetched from a lower level of the memory hierarchy, so negatively impacting on performance and energy consumption. As opposite, if the capacitance is too high, energy would be wasted without bringing performance benefits. This paper identifies the optimal capacitance for a given processor frequency. To this end, the tradeoff between performance and energy consumption of a macrocell-based cache has been evaluated varying the capacitance and frequency. Experimental results show that, compared to a conventional cache, performance losses are lower than 2% and energy savings are up to 55% for a cache with 10 fF capacitors and frequencies higher than 1 GHz. In addition, using trench capacitors, a 4-bit macrocell reduces by 29% the area of four conventional SRAM cells.

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Section: Areamentioning

confidence: 85%

Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches

Valero

Sahuquillo

Lorente

et al. 2012

IEEE Trans. VLSI Syst.

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“…Therefore, the number of banks has been set to eight across all the experiments. This number of banks is reasonable, since it is common to find designs having more banks in the literature [8]. Finally, since one bank only can perform one swap operation at a given time, the number of banks also matches the number of intermediate buffers.…”

Section: Performance Evaluationmentioning

confidence: 99%

Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches

Valero

Petit

Sahuquillo

et al. 2012

IEEE Trans. Comput.

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Abstract-SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy since there are no paths within the cell from Vdd to ground. Recently, DRAM cells have been embedded in logic-based technology (eDRAM), thus overcoming the speed limit of typical DRAM cells. In this paper, we propose a hybrid n-bit macrocell that implements one SRAM cell and n-1 eDRAM cells. This cell is aimed at being used in an n-way set-associative first-level data cache. Architectural mechanisms (e.g., special writeback policies) have been devised to completely avoid refresh logic. Performance, energy, and area have been analyzed in detail. Experimental results show that using typical eDRAM capacitors, and compared to a conventional cache, a four-way set-associative hybrid cache reduces both energy consumption and area up to 54% and 29%, respectively, while having negligible impact on performance (less than 2%).

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“…This number of banks is reasonable and it is common to find other cache designs in the literature with much more banks and the same or lower bank storage capacity [5] [13]. Nevertheless, such a number of banks can be reduced by implementing the eDRAM banks with more than two ways.…”

Section: Hybrid Lcache Designmentioning

confidence: 99%