(110) channel, SiON gate-dielectric PMOS with record high I&lt;sub&gt;on&lt;/sub&gt;=1 mA/&amp;#x003BC;m through channel stress and source drain external resistance (R&lt;sub&gt;ext&lt;/sub&gt;) engineering

Yang, Bin; Waite, A.M.; Yin, Haizhou; Yu, Jung‐Suk; Black, L.; Chidambarrao, D.; Domenicucci, A.; Wang, X.; Ku, S.H.; Wang, Y.; Meer, H. van; Kim, B.; Kim, S.D.; Tabakman, K.; Pal, Rohit; Nummy, Karen; Greene, B.; Fisher, Philip A.; Liu, J.; Liang, Qi; Holt, J.; Narasimha, S.; Luo, Zhijiong; Utomo, H.; Chen, X.; Park, D.; Sung, C.Y.; Wachnik, R.; Freeman, G.; Schepis, D.; Maciejewski, E.; Khare, Mukesh; Leobandung, E.; Luning, S.; Agnello, P.

doi:10.1109/iedm.2007.4418927

Cited by 6 publications

(5 citation statements)

References 0 publications

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“…To compare these s-Ge PFETs to state-of-the-art Si channel PFETs, we compare the G CH derived by using the dR ON /dL G from recent publications [8] to our present results. We directly obtain G CH at V G − V T = −0.7 V for s-Si using 1) compressive stress liners (CSL) and 2) CSL used with embedded SiGe source/drain (CSL + SiGe) from [8,Figs.…”

Section: (B) and (C)mentioning

confidence: 91%

“…It is important to point out, however, that these s-Ge devices are suboptimal in many regards, whereas the s-Si devices [8] are highly optimized. For example, XRD analysis indicated that, at most, the strain in the Ge channel is only 0.5%, and it has been shown that the strain should be greater than 1% to see significant hole mobility improvement [11].…”

Section: (B) and (C)mentioning

confidence: 98%

“…We directly obtain G CH at V G − V T = −0.7 V for s-Si using 1) compressive stress liners (CSL) and 2) CSL used with embedded SiGe source/drain (CSL + SiGe) from [8,Figs. 6 and 9].…”

Section: (B) and (C)mentioning

confidence: 99%

“…As Ge was being explored over the past few years, local Si straining techniques (using embedded SiGe and nitride stressor layers) were optimized to a degree that a four-fold increase in mobility over unstrained Si PFETs could be realized [6], [7]. Recently, Si PFETs with drain-currents reaching the 1-mA/µm level have been demonstrated by combining process-induced strain with (110) Si or high-κ/metal-gate stack [8], [9]. In light of these achievements, the questions for the role of Ge as a p-channel alternative are the following: 1) Can Ge still be competitive against strained Si (s-Si); and 2) can Ge retain its performance at short gate lengths?…”

Section: Introductionmentioning

confidence: 99%

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Mobility Scaling in Short-Channel Length Strained Ge-on-Insulator P-MOSFETs

Bedell

Majumdar

Ott

et al. 2008

IEEE Electron Device Lett.

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The hole transport characteristics in partially strained (0.5%) Ge p-channel MOSFETs formed on silicongermanium-on-insulator (SGOI) substrates were investigated for gate lengths down to 65 nm. We demonstrate that high hole mobility is maintained down to the shortest channel lengths. The channel conductance from these devices is measured and compared to state-of-the-art high-performance Si channel P-MOSFETs.

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Section: (B) and (C)mentioning

confidence: 91%

Section: (B) and (C)mentioning

confidence: 98%

“…We directly obtain G CH at V G − V T = −0.7 V for s-Si using 1) compressive stress liners (CSL) and 2) CSL used with embedded SiGe source/drain (CSL + SiGe) from [8,Figs. 6 and 9].…”

Section: (B) and (C)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Mobility Scaling in Short-Channel Length Strained Ge-on-Insulator P-MOSFETs

Bedell

Majumdar

Ott

et al. 2008

IEEE Electron Device Lett.

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“…In addition, process optimization of pre-clean before eSiGe growth, the epitaxial process, and fill levels relative to the channel Si surface (such as flush-fill, under-fill, or over-fill) are all critical to maximize the eSiGe stress benefit. By careful engineering all aspects of the eSiGe process, a more than 2× pMOS mobility enhancement and 20%-30% drive current improvement were achieved for a 45-nm pMOS as reported by IBM and AMD [17,20].…”

Section: Embedded Sige (Esige)mentioning

confidence: 76%

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Yang

Cai

2011

Sci. China Inf. Sci.

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The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies. CitationYang B, Cai M. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci China Inf Sci, 2011, 54: 946-958,

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