Comprehensive study of S/D engineering for 32nm node CMOS in direct silicon bonded (DSB) technology

Yasutake, N.; Nomachi, Akiko; Itokawa, Hiroshi; Morooka, T.; Zhang, L.; Fukushima, Takashi; Harakawa, H.; Mizushima, Ichiro; Azuma, A.; Toyosihma, Y.

doi:10.1016/j.sse.2009.03.016

Cited by 2 publications

(1 citation statement)

References 8 publications

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“…This has led to our current pursuit of using (1 1 0) as an alternative wafer source, supported by the additional benefit that the hole mobility in the (1 1 0) channel surface is the highest of any silicon orientations [22]. This high hole mobility has led to the development of (1 1 0) pMOSFETs [23][24][25][26][27][28][29] and the use of direct silicon bonded (DSB) hybrid orientation technology (HOT) as a potential candidate for next-generation CMOS technology [30].…”

Section: Introductionmentioning

confidence: 99%

Fabrication of microstructured silicon (µs-Si) from a bulk Si wafer and its use in the printing of high-performance thin-film transistors on plastic substrates

Lee

Ahn

Motala

et al. 2010

J. Micromech. Microeng.

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In this paper, we report a new fabrication route to generate microstructured, single-crystalline silicon (μs-Si) ribbons using (1 1 0) silicon. Two different methods were explored for producing these printable structures. This work also introduces a second-process innovation in the fabrication of microstructured semiconductor objects for printed large-area circuits, namely the direct integration of a high-quality, thermally grown silicon dioxide (SiO 2 ) layer for use as a gate dielectric in top-gate metal-oxide-silicon field effect transistors. We also demonstrate and characterize a soft, conformable lamination process that considerably enhances the mechanical stability of devices printed on plastic, allowing bending radii as small as 0.8 cm. These structures enable a reduction of the bending strains localized at the device interface. These improvements were fully characterized by finite element simulations of the strain distribution present in a descriptive model of the multilayer laminated circuit.

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