32nm general purpose bulk CMOS technology for high performance applications at low voltage

Arnaud, F.; Liu, J.; Lee, Y.M.; Lim, Kwan-Yong; Kohler, S.; Chen, J.; Moon, Byungsoo; Lai, Chien-You; Lipiński, M.; Sang, Ling; Guarin, F.; Hobbs, Chris; Ferreira, Paulo; Ohuchi, K.; Li, J.; Zhuang, Hao; Mora, P.; Zhang, Q.; Nair, Deleep R.; Lee, D.H.; Chan, K.; Satadru, S.; Yang, S.; Koshy, J.; Hayter, W.; Zaleski, M.; Coolbaugh, D.; Kim, H.W.; Ee, Yen-Jie; Sudijono, J.; Thean, A.; Sherony, M.; Samavedam, S.; Khare, Mukesh; Goldberg, C.; Steegen, An

doi:10.1109/iedm.2008.4796771

Cited by 34 publications

(8 citation statements)

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“…As an example, the SRAM cell static noise margin (SNM) trend in Fig. 5 illustrates that a 22nm HK/MG device may still have adequate SNM [1,6,[8][9][11][12]. PTM HK/MG SNM is below the average of published data at 22nm node.…”

Section: IImentioning

confidence: 96%

Pathfinding for 22nm CMOS designs using Predictive Technology Models

Zhao

Cao

et al. 2009

2009 IEEE Custom Integrated Circuits Conference

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Traditional IC scaling is becoming increasingly difficult at the 22nm node and beyond. Dealing with these challenges increase product development cycle time. For continued CMOS scaling, it is essential to start design explorations in new process nodes as early as possible. Such an effort requires having Predictive Technology Models, which bridge technological and design practices, in order to assess the performance impact of future key modules. In this paper we propose a strategy that enables simultaneous investigation of advanced process and design concepts. Based on a customized predictive methodology and silicon data at 90-45nm nodes, compact transistor and interconnect models are developed for the next generation CMOS technology. We capture the heuristic device behavior during the scaling, which helps us to gain key insights that allow us to make tradeoffs of circuit performance metrics for next technology node. I.INTRODUCTION CMOS technology scaling is increasingly challenged by physics and manufacturing limits at 22nm and beyond [1]. These challenges reduce the predictability of circuit performance and increase the development cycle for new IC products. Continued CMOS scaling, it requires comprehending the technology impacts and capabilities as early as possible. This enables identification of potential issues, allows adaptive design decisions up front, and guarantees managing the time to market. Objecting such early stage exploration requires Predictive Technology Models (PTM) to assess performance trends, evaluate key modules before Silicon is ready, and facilitates the development of future CMOS technology [2][3].This work proposes such a predictive strategy to enable simultaneous exploration of low power CMOS process and design concepts. We incorporate the general PTM methodology [2][3][4], with customized enhancements of transistor-level and interconnect-level physical effects [1]. These customized PTM models are systematically calibrated to 90-45nm Poly/SiON silicon data and published high-k/metal gate (HK/MG) information. Section II briefly presents the predictive methodology. We leverage these predictive models to quantify projections of various behaviors of CMOS devices, interconnect, and representative design modules, such as ring oscillator (RO), standard cell and SRAM for the 22nm node. The results reveal the trends, potential, and limits of technology scaling, and provide important guidance and insight into process and design choices (Section III).

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Section: IImentioning

confidence: 96%

Pathfinding for 22nm CMOS designs using Predictive Technology Models

Zhao

Cao

et al. 2009

2009 IEEE Custom Integrated Circuits Conference

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“…Based on recent publications [17]- [21], the dimensions for 22-nm-node 6-T SRAM cells were selected for this study. The cell layout parameters are summarized in Table III.…”

Section: A Nominal Cell Designmentioning

confidence: 99%

Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

Shin

Cho

Tsukamoto

et al. 2010

IEEE Trans. Electron Devices

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Abstract-The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyzed for FD-SOI versus bulk SRAM cells. Iso-area and iso-yield comparisons are then made to determine the yield and cell-area benefits of FD-SOI technology, respectively. Finally, the minimum operating voltages (V min ) required for FD-SOI and bulk SRAM cells to meet the six-sigma yield requirement are compared.

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“…Layout dimensions for 22nm (25nm drawn gate length) 6-T SRAM cells were selected based on recent publications [6][7][8][9][10] and are summarized in Table I for a conventional notched cell layout. The quasi-planar bulk MOSFET design was optimized via 3-D device simulations to achieve the highest I ON for I OFF = 3nA/um, at V dd = 1V: electrical channel length (distance between the points where the source/drain doping profiles fall to 2×10 19 cm -3 ) L eff = 27nm; effective oxide thickness EOT = 9Å; source/drain extension junction depth X J,ext = 10nm.…”

Section: Nm Bulk Sram Cell Design Studymentioning

confidence: 99%

Tri-gate bulk CMOS technology for improved SRAM scalability

Shin

Nikolić

Liu

et al. 2010

2010 Proceedings of the European Solid State Device Research Conference

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-A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, quasi-planar bulk CMOS technology can facilitate voltage scaling. It also provides a means to achieve high yield with a notch-less 6T-SRAM cell layout, to facilitate area scaling. I. INTRODUCTIONA challenge for continued SRAM scaling is threshold voltage (V T ) mismatch due to process-induced variations [1], which degrades the minimum operating voltage (V min ) of an SRAM array [2]. To address this challenge, an improved transistor design that provides for reduced short-channel effects (i.e., improved gate control over the channel potential) is required. The quasi-planar tri-gate bulk MOSFET [3] is an example of such a design; it utilizes a gate electrode that is physically wrapped around the top portion of the channel region to provide for greater capacitive coupling between the gate and the channel region [4]. In this work, a timed etch in dilute hydrofluoric (HF) acid solution is used to recess the isolation oxide prior to gate-stack formation, to form quasiplanar bulk MOSFETs using an otherwise conventional fabrication process flow.Improvements in transistor performance and SRAM yield are demonstrated in an early 28nm CMOS technology. The benefits of quasi-planar bulk MOSFET technology for voltage and area scaling are then assessed using three-dimensional (3-D) device simulations with atomistic doping profiles and analytical modeling to estimate 6T-SRAM cell yield for 22nm CMOS technology.

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32nm general purpose bulk CMOS technology for high performance applications at low voltage

Cited by 34 publications

References 0 publications

Pathfinding for 22nm CMOS designs using Predictive Technology Models

Pathfinding for 22nm CMOS designs using Predictive Technology Models

Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

Tri-gate bulk CMOS technology for improved SRAM scalability

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