Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

Abstract

Abstract-The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyzed for FD-SOI versus bulk SRAM cells. Iso-area and iso-yield comparisons are then made to determine the yield and cell-area benefits of FD-SOI technology, respectively. Finally, the minimum operating voltages (V min ) required for FD-SOI and bulk SRAM cells to meet the six-sigma yield requirement are compared.

(Invited) Overview of Fully Depleted SOI Technology and Circuit Benefits

“…The typical bulk countermeasures of increasing V DD , or increasing the channel length and width to compensate for the V T variability is no longer necessary. At the same cell size, FDSOI makes possible to gain 200mV to 300mV in Vmin compared to the bulk cell (17,18). The operation regime at V DD <0.8V is very attractive for mobile hand held applications.…”

State-of-the-art silicon device miniaturization technology and its challenges

“…To surmount the LER-induced V TH variation, a device structure that is strongly immune to short-channel effects should be used. For example, multi-gate devices such as FinFETs and tri-gate MOSFETs [6,7] and ultra-thin-body devices such as Fully Depleted Silicon-On-Insulator (FD-SOI) MOSFETs [8] are good candidates to overcome the LER-induced V TH variation, due primarily to their improved gate-to-channel capacitive coupling (in comparison with conventional planar bulk MOSFETs).…”

Large energy-loss straggling of swift heavy ions in ultra-thin active silicon layers

“…While the active silicon layers of those advanced structures can be ultra-thin, even on the order of a few nanometers. [11][12][13][14][15][16][17][18][19][20] Considering that those ultra-thin silicon films contain only a few tens of silicon atomic layers, i.e., worse statistics than earlier thin films, the energy-loss straggling by the direct ionization process in nano films will be more pronounced and needs detailed analysis. However, few data has been published dealing with the variations of deposited energy in ultra-thin active silicon layers and the potential inadequacies of current error rate prediction methods.…”