No abstract

No abstract

No abstract

No abstract

We've developed Bit Cost Scalable (BiCS) flash technology as a three-dimensional memory for the future ultra high density storage devices, which extremely reduces the chip costs by vertically stacking memory arrays with punch and plug process. We've advanced it into Pipe-shaped BiCS flash memory introducing Ushaped NAND string structure, to improve operation window, speed and reliability. 32 G bit test chips with 16 stacked layers by 60nm P-BiCS flash process have been fabricated, and the functionality of Multi-Level-Cell (MLC) operation has been successfully demonstrated. P-BiCS is the most promising candidate of three-dimensional ultra high density data storage memories.

No abstract

Fin gate array transistor (Fin-Arrayen fabricated on bulk silicon substrate is applied to the DRAM cell with the deep trench @TI capacitor. Fin-ArrayFET is designed for the 130 nm technology node and beyond by using the 3-D device simulator (HyDeLEOS) and proccss simulator (HySyProS) ['I. It is demonstrated that the on-current of Fin-Array-FET is 62 pA/cell that is about 1.7 times as much as conventional planer array FET, keeping the off-current 0.1 fNcell. It is also demonstrated that Fin-Array-FET on bulk silicon substrate can relieve of the retention degradation because the channel baron doping can be reduced to more than one order compared to the conventional planer array FET.

No abstract