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Fin gate array transistor (Fin-Arrayen fabricated on bulk silicon substrate is applied to the DRAM cell with the deep trench @TI capacitor. Fin-ArrayFET is designed for the 130 nm technology node and beyond by using the 3-D device simulator (HyDeLEOS) and proccss simulator (HySyProS) ['I. It is demonstrated that the on-current of Fin-Array-FET is 62 pA/cell that is about 1.7 times as much as conventional planer array FET, keeping the off-current 0.1 fNcell. It is also demonstrated that Fin-Array-FET on bulk silicon substrate can relieve of the retention degradation because the channel baron doping can be reduced to more than one order compared to the conventional planer array FET.

Program and erase operation on NAND-string of Bit-Cost Scalable (BiCS) flash memory has been successfully achieved. High boost efficiency of floating pillars and ONON (block oxide/charge SiN/tunnel oxide/tunnel SiN) structure as a memory film stack improve disturbance characteristics enough to realize tera-bit density of three dimensional flash memory. BiCS flash memory has become a more promising candidate for ultra high density memory.