Fin-Array-FET on bulk silicon for sub-100 nm trench capacitor DRAM

Katsumata, Ryoichi; Tsuda, Nobuo; Idebuchi, J.; Kondo, Masaki; Aoki, Naofumi; Ito, S.; Yahashi, K.; Satonaka, T.; Morikado, M.; Kito, M.; Kido, M.; Tanaka, Tomoharu; Aochi, Hideaki; Hamamoto, T.

doi:10.1109/vlsit.2003.1221086

Cited by 12 publications

(8 citation statements)

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“…Researchers have proposed several different devices for a bitcell transistor to reduce leakages [21][22][23][24][25][26][27][28]. Samsung proposed the recessed channel array transistor (RCAT) with 88 nm DRAM technology [21] and scaling RCAT down to 50 nm process [22].…”

Section: Transistor Model and Scalingmentioning

confidence: 99%

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3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model

Park

Davis

Franzon

2019

IEEE Trans. Circuits Syst. I

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Three-dimensional stacked DRAM technology has emerged recently. Many studies have shown that 3D DRAM is most promising solutions for future memory architecture to fulfill high bandwidth and high-speed operation with low energy consumption. It is necessary to explore 3D DRAM design space and find the optimum DRAM architecture in different system needs. However, a few studies have offered models for power and access latency calculations of DRAM designs in limited ranges. This has led to a growing gap in knowledge of the area, timing, and energy modeling of 3D DRAMs for utilization in the design process of processor architectures that could benefit from 3D DRAMs. This paper presents a circuit level DRAM Area, Timing, and Energy model (DATE) which supports 3D DRAM design with TSV. DATE provides front-end and back-end DRAM process roadmap from 90 nm to 16 nm node and provides a broader range 3D DRAM design model along with emerging transistor device. DATE is successfully validated against several commodity planar and 3D DRAMs and published prototype DRAMs with emerging device. Energy verification has a mean error of about -5% to 1%, with a standard deviation of up to 9.8%. Speed verification has a mean error of about -13% to -27% and a standard deviation of up to 24%. In the case of the area, the bank has a mean error of -3% and the whole die has a mean error of -1%. The standard deviation for area is up to 4.2%. In the case study, we demonstrate that 1Gb DDR3 DRAM designs achieve up to about 0.7 Gb/sec data throughput and energy efficiency of 510 bit/nJ using 3D design options with 16 nm DRAM technology.

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Section: Transistor Model and Scalingmentioning

confidence: 99%

“…SRCAT provides more recessed channel effect than RCAT [23]. FinFET or its hybrid are also studied as a bitcell transistor in DRAMs [25][26][27]30]. Fin-FETs have a more extensive channel width compared to a planar transistor which helps to suppress short channel effect.…”

Section: Transistor Model and Scalingmentioning

confidence: 99%

3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model

Park

Davis

Franzon

2019

IEEE Trans. Circuits Syst. I

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“…In order to overcome the array FET constraints, trench isolated transistor using sidewall gates (TIS) or fin-array-FET approach can be adopted to improve the transistor performance as in the case of SOI transistors [1][2][3][4]. Fig.…”

Section: Tis/fin/sgt Drammentioning

confidence: 99%

Advanced memory concepts for DRAM and nonvolatile memories

Horiguchi

2006

Solid-State Electronics

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“…As planar channel DRAM cell size shrinks to sub-100 nm, it becomes difficult to control the Short Channel Effect (SCE) and increase of junction leakage current and gate-induced drain leakage (GIDL) currents becomes critical problem [1]- [7]. Bulk FinFETs have been considered as one of the most promising candidates for the sub-50 nm DRAM cell transistor because of short channel effects immunity [2]- [5].…”

Section: Introductionmentioning

confidence: 99%