Fin gate array transistor (Fin-Arrayen fabricated on bulk silicon substrate is applied to the DRAM cell with the deep trench @TI capacitor. Fin-ArrayFET is designed for the 130 nm technology node and beyond by using the 3-D device simulator (HyDeLEOS) and proccss simulator (HySyProS) ['I. It is demonstrated that the on-current of Fin-Array-FET is 62 pA/cell that is about 1.7 times as much as conventional planer array FET, keeping the off-current 0.1 fNcell. It is also demonstrated that Fin-Array-FET on bulk silicon substrate can relieve of the retention degradation because the channel baron doping can be reduced to more than one order compared to the conventional planer array FET.
In this study, the potential of HfSiON as the node dielectric of deep-trench (DT) capacitors was investigated for the first time. It was found out that a uniform thickness and a uniform depth profile of each component in DT can be obtained by the ALD process which utilizes the catalytic effect of the Hf precursor and Si precursor. In addition, the mechanism underlying leakage current was analyzed and it was revealed that residual carbons in the film contribute to the Poole–Frenkel current through the film. On the basis of these findings, we propose the sequential high-pressure ozone treatment (SHO) and Al2O3/HfSiON/Si3N4 stack for DT applications. Finally, the DT capacitors of 65-nm-node embedded dynamic random-access memory (eDRAM) were fabricated and a capacitance enhancement of 50% from the conventional dielectric (NO) was obtained at the same leakage current.
We developed a less layout-dependent epitaxially grown SiGe (eSiGe) source/drain (S/D) technique for pFET. We found that the effective stressor region of eSiGe existed only near the channel and that the volume effect of eSiGe was small. On the basis of this mechanism, a new recess RIE and a new epitaxial growth technology were developed, so that the gate-pitch dependence, S/D length dependence and channel width dependence were extremely reduced. In addition, we succeeded in increasing the drive current by improving the eSiGe structure and the impurity profile. We also obtained a high drive current of 750 uA/um at Vdd=1V, Ioff=100nA/um.
ALD HfSiOx was applied to the node dielectric of deep trench (DT) capacitors of the 65nm node embedded DRAM (eDRAM) for the first time. As a result, capacitance enhancement of 30% from the conventional dielectric (NO) was achieved at the same level of leakage current. The main features of our ALD process are 1) a uniform thickness and depth profile of each component in DT by taking advantage of a catalytic effect of the precursors and 2) a reduced amount of impurities in the film without causing any degradation of step coverage.
For the first time, a novel CMOSFET structure in substrate strained-Si of <100>-channel on rotated wafers is presented. Low Ge concentration (10%) of SiGe layer is used in order to suppress the Vth shift and the mobility reduction caused by high channel doping. We applied Si selective epitaxial growth on recessed S/D region in SiGe layer, which is effective to induce high tensile stress and reduce S/D resistance. In strained Si NMOS, 15% performance improvement is achieved. Moreover, additive stress by using tensile CESL can further improve the drive current. In strained Si PMOS, 25% performance improvement is achieved in both narrow and wide channel device.
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