Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

Tanaka, Hidetake; Kido, M.; Yahashi, K.; Oomura, M.; Katsumata, Ryoichi; Kito, M.; Fukuzumi, Y.; Sato, Manabu; Nagata, Yoshihiko; Matsuoka, Yasuo; Iwata, Y.; Aochi, Hideaki; Nitayama, A.

doi:10.1109/vlsit.2007.4339708

Cited by 481 publications

(240 citation statements)

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“…The simple process and improved reliability of the charge trapping layer enables the SONOS device to be applied in three-dimensional (3D) stacked structure for ultra-high density flash memory. [4][5][6][7] To achieve high performance with fast program or erase characteristics, new structures for the SONOS device have been proposed with the analysis of the charge injection mechanism. Formation of dopant-segregated Schottky-barrier on the source/drain increases program speed by the high efficiency of charge injection originating from sharp band bending at the source/drain.…”

confidence: 99%

A SONOS device with a separated charge trapping layer for improvement of charge injection

Ahn

Moon

et al. 2017

AIP Advances

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A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.

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confidence: 99%

A SONOS device with a separated charge trapping layer for improvement of charge injection

Ahn

Moon

et al. 2017

AIP Advances

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“…Moreover, the formation of such shallow junctions becomes a serious concern with 3-dimensional (3D) multi-stacking integration due to the large thermal budget required. For this reason, a "junction-free transistor" based on junction-free virtual S/D for NAND Flash memory was previously reported, and the concept was applied to other types of 3D integrated Flash memory such as Bit Cost Scalable (BiCS) memory (Tanaka et al, 2007), Vertical-Stacked-Array-Transistor (VSAT) memory (Kim et al, 2009), and Terabit Cell Array Transistor (TCAT) memory (Jang et al, 2009), among others (Hubert et al, 2009). However, it can be expected that current flowing through a string of NAND Flash memory will be significantly degraded by pre-existing high resistance regions, i.e., undoped source/drain (S/D) regions, despite that these regions can be transformed into low 191 resistance regions via an inversion process by fringing the field from the gate.…”

Section: Junctionless Mosfetsmentioning

confidence: 99%

Source and Drain Junction Engineering for Enhanced Non-Volatile Memory Performance

Choi¹,

Choi²

2011

Flash Memories

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“…Rather than stacking individual dies, one can also try to stack layers of memory elements on top of each other on the same base wafer [12]. One does save substrate material this way, but the process is not inherently cheaper, since again tens of the highest resolution lithography steps are required.…”

Section: The Challenge In Non-volatile Data Storagementioning

confidence: 99%

Self-Assembled Three-Dimensional Non-Volatile Memories

et al. 2010

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Abstract:The continuous increase in capacity of non-volatile data storage systems will lead to bit densities of one bit per atom in 2020. Beyond this point, capacity can be increased by moving into the third dimension. We propose to use self-assembly of nanosized elements, either as a loosely organised associative network or into a cross-point architecture. When using principles requiring electrical connection, we show the need for transistor-based cross-talk isolation. Cross-talk can be avoided by reusing the coincident current magnetic ring core memory architecture invented in 1953. We demonstrate that self-assembly of three-dimensional ring core memories is in principle possible by combining corner lithography and anisotropic etching into single crystal silicon.

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Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

Cited by 481 publications

References 0 publications

A SONOS device with a separated charge trapping layer for improvement of charge injection

A SONOS device with a separated charge trapping layer for improvement of charge injection

Source and Drain Junction Engineering for Enhanced Non-Volatile Memory Performance

Self-Assembled Three-Dimensional Non-Volatile Memories

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