BiCS Flash as a Future 3D Non-Volatile Memory Technology for Ultra High Density Storage Devices

Aochi, Hideaki

doi:10.1109/imw.2009.5090581

Cited by 34 publications

(14 citation statements)

References 5 publications

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“…Multiple holes are drilled through the stacks and filled with poly-silicon in order to form a series of vertically-arranged NAND Flash memory cells. Bitline Selectors (BLS) and Bitlines (BL) contacts are on top of the structure [21]. Each cell in the BiCS architecture works in depletion-mode [22] since the poly-silicon constituting the body of the transistor is lightly n-doped with a uniform profile or even left un-doped.…”

Section: Bics Architecturementioning

confidence: 99%

Architectural and Integration Options for 3D NAND Flash Memories

Micheloni

Crippa²,

Zambelli

et al. 2017

Computers

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Nowadays, NAND Flash technology is everywhere, since it is the core of the code and data storage in mobile and embedded applications; moreover, its market share is exploding with Solid-State-Drives (SSDs), which are replacing Hard Disk Drives (HDDs) in consumer and enterprise scenarios. To keep the evolutionary pace of the technology, NAND Flash must scale aggressively in terms of bit cost. When approaching ultra-scaled technologies, planar NAND is hitting a wall: both academia researchers and industry worked to cope with this issue for several decades. Then, the 3D integration approach turned out to be the definitive alternative by eventually reaching mass production. This review paper exposes several 3D NAND Flash memory technologies, along with their related integration challenges, by showing their different layouts, scaling trends and performance/reliability features.

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Section: Bics Architecturementioning

confidence: 99%

Architectural and Integration Options for 3D NAND Flash Memories

Micheloni

Crippa²,

Zambelli

et al. 2017

Computers

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“…PBICS architecture [14] is a derivation of bit-cost scalable (BiCS) [15,16]; both are based on a vertical channel GAA device. The PBICS structure is composed of two pillars that are shorted at the bottom side by a pipe connection ( Figure 6).…”

Section: Pipe-shaped Bit Cost Scalable (Pbics) Architecturementioning

confidence: 99%

3D NAND Flash Based on Planar Cells

Silvagni¹

2017

Computers

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Abstract:In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a "punch-and-plug" process-with gate-all-around (GAA) cell devices-against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production.

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“…Holes are punched through the entire stack and plugged with poly-silicon, thus forming a series of vertical memory cells connected in a NAND architecture. At the top of the structure we have Bit Line Selectors (BLS's) and Bitlines (BLs) [9].…”

Section: Bicsmentioning

confidence: 99%

“…4.8 and 4.9 the basic building block of BiCS memory is split in different sections in order to provide a greater level of details for the different elements [6,9]. Cell's structure is clearly visible in the Middle section where the reader can find all the layers seen in Fig.…”

Section: Bicsmentioning

confidence: 99%