Bit Cost Scalable (BiCS) technology for future ultra high density memories

Nitayama, A.; Aochi, Hideaki

doi:10.1109/vlsi-tsa.2013.6545626

Cited by 18 publications

(12 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The vertical poly-Si TFT is used as a memory transistor in the 3D NAND Flash memory, BICS, as shown in Fig. 23 [52]. The BICS is expected as a next generation high-density NAND Flash memory.…”

Section: D-stacked Cmos Image Sensormentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

View full text Add to dashboard Cite

3D integration technology is the key for future LSIs with highperformance, low-power and multi-functionality. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology has been discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.

show abstract

Section: D-stacked Cmos Image Sensormentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…One variant of this concept has reached the market recently [71] and more devices are expected in the near future. Besides NAND Flash, the general concept can also be extended to other devices like resistive RAM (RRAM) [72]. Although not all applications can benefit from the nanowire geometry in the same way the charge trapping memory cell does, in most cases a nanowire like structure will be the result of this type of integration scheme.…”

Section: Electron Devices Based On Silicon Nanowiresmentioning

confidence: 99%

Silicon Nanowires: Fabrication and Applications

Mikolajick

Weber

2015

NanoScience and Technology

View full text Add to dashboard Cite

Due to the high surface to volume silicon ratio and unique quasi onedimensional electronic structure, silicon nanowire based devices have properties that can outperform their traditional counterparts in many ways. To fabricate silicon nanowires, in principle there are a variety of different approaches. These can be classified into top-down and bottom-up methods. The choice of fabrication method is strongly linked to the target application. From an application point of view, electron devices based on silicon nanowires are a natural extension of the downscaling of a silicon metal insulator semiconductor transistor. However, the unique properties also allow implementing new device concepts like the junctionless transistor and new functionalities like reconfigurability on the device level. Sensor devices may benefit from the high surface to volume ratio leading to a very high sensitivity of the device. Also, solar cells and anodes in Li-ion batteries can be improved by exploiting the quasi one-dimensionality. This chapter will give a review on the state-of-the-art of silicon nanowire fabrication and their application in different types of devices.

show abstract

“…To enlarge the capacity, 3D-NAND flash memory is developed by stacking word-line (WL) layers (Fig. 1) [1].…”

Section: Introductionmentioning

confidence: 99%

Error Suppression of Last-Programmed Word-Line for Real Usage of 3D-NAND Flash Memory

Kojima

Takeuchi

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

Blocks of 3D-NAND flash memory are programmed in order of WL. In real usage of 3D-NAND flash memory, a block contains both programmed WLs and not programmed WLs because the programmed data do not always fill the block. In the block, the last data are programmed at 'lastprogrammed WL' where the upper WL is not programmed. The last programmed data are supposed to have high reliability owing to shorter data-retention time. However, when upper WL is not programmed, BER of last-programmed WL largely increases because upper WL has less electrons and causes lateral charge migration. To suppress the errors at last-programmed word-line, this paper proposes Last-programmed Word-line Protection (LWLP). Proposed LWLP suppresses BER by 37% at last-programmed WL and extends data-retention time by more than 4 times.

show abstract

Bit Cost Scalable (BiCS) technology for future ultra high density memories

Cited by 18 publications

References 1 publication

Recent progress in 3D integration technology

Recent progress in 3D integration technology

Silicon Nanowires: Fabrication and Applications

Error Suppression of Last-Programmed Word-Line for Real Usage of 3D-NAND Flash Memory

Contact Info

Product

Resources

About