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SUMMARYIn analog signal-processing applications, settling performance of the employed operational amplifiers (opamps) is usually of great matter. Under low-voltage environment of modern technologies where only a few transistors are allowed to be stacked, three-stage amplifiers are gaining more interest. Unfortunately, design and optimization of three-stage opamps based on settling time still suffer from lack of a comprehensive analysis of the settling behavior and closed-form relations between settling time/error and other parameters. In this paper, a thorough analysis of the settling response of three-stage nestedMiller-compensated opamps, including linear and non-linear sections, is presented. This analysis leads to a design methodology which determines the circuit requirements for desired settling time/error. Based on settling time, it allows optimizations in power consumption and area.

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A generic nano‐power voltage and current reference topology, which takes advantage of the unequal threshold voltage (VnormalTH) of two MOSFETs in subthreshold region, is developed to provide reliable bias and reference signals for the analogue integrated blocks used in the Internet‐of‐Things applications. The new architecture is a self‐powered four‐transistor topology with a single temperature‐insensitive resistor, generating both temperature‐independent voltage and current without any operational amplifier or bias network. Instead, the resistor defines the absolute value of the current reference (InormalREF) which supplies the core devices. The circuit is designed and simulated for a target current reference of 7.50 nA in 0.18 µm CMOS process, and achieves a worst‐case temperature coefficient (TC) of 59.47 ppm/°C over a temperature range from −40 to 125°C and 1.8 V voltage supply. The average voltage reference (VnormalREF) is 346 mV, and the worst‐case TC of different corners is 21.98 ppm/°C. The nominal current consumption is twice the InormalREF (15 nA) regardless of the supply and temperature, and can be scaled down by reducing the desired current reference.

Summary Advanced multistage amplifiers suffer from load‐dependent stability issues, which limit the load capacitor range they can drive. In this work, the concept of global impedance attenuation (GIA) network is introduced to improve an amplifier's stability in the presence of significant load capacitor variations. Composed of multiple parallel resistor‐capacitor (RC) branches, the equivalent high‐frequency output impedance of gain stages is shaped by the GIA network such that a desired frequency spectrum is obtained over a wide range of load capacitor. The parasitic poles at the output of the gain stages are nullified by the proposed network, thereby simplifying the amplifier's transfer function and reducing the minimum load capacitor it can drive. The idea is applied to design a three‐stage operational transconductance amplifier (OTA) with cascode global impedance attenuation (CGIA). Small‐signal analysis shows that the OTA is stable regardless of the load capacitor, and it can drive very small to ultra‐large load capacitors. This feature is verified by the post‐layout simulations of a CGIA amplifier in 0.18‐μm complementary metal‐oxide semiconductor (CMOS) process. The core occupies a die area of 0.0053 mm2 while consuming a static current of 10.97 μA from 1.8‐V voltage supply. The unity‐feedback configuration is unconditionally stable for any load capacitor higher than 10 pF. To the best of our knowledge, this corresponds to the widest range of load capacitance reported for prior‐art three‐stage amplifiers.

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An area-efficient amplifier topology is presented for three-stage amplifiers driving ultralarge load capacitor with reduced power consumption. It contains two high-speed ac feedback loops made from embedded current buffers and smallsize compensation capacitors, which pushes the nondominant complex poles to very high frequencies. To further improve the stability, a local impedance damping block is embedded. At the higher frequencies, it suppresses the high resistive property at the second-stage output, thereby increasing the damping factor of the complex poles and improving the overall gain margin. For identical bandwidth, the overall silicon area of the on-chip compensation capacitor is therefore decreased, leading to enhanced small-signal and large-signal performance metrics. Coined dual loop cascode-Miller compensation with damping factor control unit, the effectiveness of the proposed approach is investigated through simulation results in 90-nm complementary metal-oxide-semiconductor (CMOS) technology. An implementation based on the proposed technique consumes a quiescent current of 17 μA from a 1.2 V voltage supply. For a load capacitance equal to 560 pF, it achieves a gain-bandwidth frequency of 4.34 MHz, an average slew-rate of 1.72 V/μs, and an average settling time of 0.52 μs, when the overall compensation capacitance is set to 1.55 pF. The proposed design can supply the load capacitors up to 35 nF.