Summary
Advanced multistage amplifiers suffer from load‐dependent stability issues, which limit the load capacitor range they can drive. In this work, the concept of global impedance attenuation (GIA) network is introduced to improve an amplifier's stability in the presence of significant load capacitor variations. Composed of multiple parallel resistor‐capacitor (RC) branches, the equivalent high‐frequency output impedance of gain stages is shaped by the GIA network such that a desired frequency spectrum is obtained over a wide range of load capacitor. The parasitic poles at the output of the gain stages are nullified by the proposed network, thereby simplifying the amplifier's transfer function and reducing the minimum load capacitor it can drive. The idea is applied to design a three‐stage operational transconductance amplifier (OTA) with cascode global impedance attenuation (CGIA). Small‐signal analysis shows that the OTA is stable regardless of the load capacitor, and it can drive very small to ultra‐large load capacitors. This feature is verified by the post‐layout simulations of a CGIA amplifier in 0.18‐μm complementary metal‐oxide semiconductor (CMOS) process. The core occupies a die area of 0.0053 mm2 while consuming a static current of 10.97 μA from 1.8‐V voltage supply. The unity‐feedback configuration is unconditionally stable for any load capacitor higher than 10 pF. To the best of our knowledge, this corresponds to the widest range of load capacitance reported for prior‐art three‐stage amplifiers.
Purpose
The purpose of this study is to discuss the effect of hybrid cascode compensation with quality factor (Q-factor) control module for the three-stage amplifiers driving ultra-large load capacitors. Compared to the present frequency compensation solutions, it extends the amplifier bandwidth by establishing an extra AC feedback pathway besides the primary pathway through the Miller capacitor, increasing the loop gain at the gain–bandwidth product (GBW) frequency by pushing to the higher frequencies the nondominant poles.
Design/methodology/approach
A Q-factor control block is used to improve the damping factor of the compensation loop with no power or area overhead, thereby reducing the frequency peaking and the undesired oscillation in the time response for small load capacitors. The Q-factor control module is realized by a tiny-size on-chip capacitor, and provides an extra feedback loop to feed the damping current back to the input stage. A left-half-plane (LHP) zero is also introduced to further improve the stability.
Findings
A prototype of the proposed amplifier is simulated in 180-nm CMOS with a quiescent current of 24-µA from 1.80-V voltage supply. It achieves a 3.98-MHz gain–bandwidth product for 500-pF load capacitor, while the overall compensation capacitor is limited to 0.5-pF and the DC gain is extended beyond 100-dB.
Originality/value
The proposed amplifier is absolutely stable for the load capacitors ranging between 80-pF and 100-nF.
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