Hybrid cascode feedforward compensation for nano-scale low-power ultra-area-efficient three-stage amplifiers

Dual loop cascode‐Miller compensation with damping factor control unit for three‐stage amplifiers driving ultralarge load capacitors

“…20 Instead of a single compensation loop used in many frequency compensation strategies such as CFCC, 15,16,18,[24][25][26][27][28][29][30][31] it contains two high-speed ac feedback loops for sensing the output voltage transients, in line with the circuit diagram shown in Figure 1F. 20 Instead of a single compensation loop used in many frequency compensation strategies such as CFCC, 15,16,18,[24][25][26][27][28][29][30][31] it contains two high-speed ac feedback loops for sensing the output voltage transients, in line with the circuit diagram shown in Figure 1F.…”

“…Simulation results of a DLCDFC prototype incorporating the new compensation strategy are addressed in section 3, to verify its advantages in terms of area and consuming power. 7,11,15,16,18,20 Furthermore, the compensation capacitors are now connected to the input of two current buffers with reduced input resistors of 1/g mC1 and 1/g mC2 , rather than the high-impedance v O1 node of the first stage output. The ac feedback loops along with the local damping factor control block all contribute to the proposed DLCDFC frequency compensation scheme, which differs in many ways from the previous frequency compensation schemes depicted in Figure 1.…”

“…Hybrid cascode feedforward compensation (HCFC) is, similarly, a modification of the CFCC scheme suited for three-stage amplifiers driving ultralarge load capacitors. 20 Instead of a single compensation loop used in many frequency compensation strategies such as CFCC, 15,16,18,[24][25][26][27][28][29][30][31] it contains two high-speed ac feedback loops for sensing the output voltage transients, in line with the circuit diagram shown in Figure 1F. The additional feedback loop increases further the complex poles frequency while requiring no additional power for implementation.…”

“…The results for HCFC amplifier thus show significant improvements in terms of power, die area, and small-and large-signal performance metrics. 20 Still, some issues and design complexities in relation to the low damping factor of nondominant poles are remained, especially with regard to the size of the parasitic capacitance at the first stage output. All these issues can be solved by using dual loop cascode-Miller compensation with damping factor control (DLCDFC) unit proposed in this article.…”

Embedded current amplifier compensation for three-stage amplifiers with large capacitive loads

“…Even so, most of the chip area is occupied by the compensation capacitors in large-capacitive-load amplifier [3]. So various frequency compensation strategies [1,3,4,5,6,7,8,9,10] are developed to reduce compensation capacitor and lower the power consumption.…”