Design of Two-Stage Miller-Compensated Amplifiers Based on an Optimized Settling Model

Analog Integr Circ Sig Process

Lotfi

Mafinezhad

2008

Self Cite

Settling behavior of operational amplifiers (opamps) is important in many analog signal-processing applications. In this paper, the analysis of single-stage opamps based on settling time has been performed. A simple yet accurate model for the settling response of firstorder opamps that modifies conventional models is proposed to revise the equations. The presented approach leads to a new simple settling-based design methodology for single-stage operational amplifiers. Circuit-level simulations demonstrate the effectiveness of the procedure.

Section: Small-signal Settling Analysismentioning

confidence: 54%

“…The proposed approach also leads to a new design methodology for single-stage opamps. Although the analysis has been performed for single-stage topologies, it can be easily extended to higher-order cases [6]. This paper is divided into five additional parts.…”

Section: Introductionmentioning

confidence: 99%

Design of low-power single-stage operational amplifiers based on an optimized settling model

Analog Integr Circ Sig Process

Lotfi

Mafinezhad

2008

Self Cite

“…High‐gain multistage amplifiers are preferred over single‐stage configurations in modern mixed‐signal processing modules with stringent accuracy requirement . These amplifiers ensure that maximum signal dynamic range is achieved under the low‐voltage supply of short‐channel metal‐oxide semiconductor (MOS) transistors since the output stage can be implemented by two transistors only.…”

Section: Introductionmentioning

confidence: 99%

“…One capacitor is eliminated safely under the framework of single Miller compensation (SMC), when the large Q ‐factor of the complex poles is reduced by the high gain factor of the second gain stage. Advanced frequency compensation schemes rely on single compensation capacitance ( C C ) in the form of cascode Miller compensation, enhancing the amplifier's performance, especially for ultra‐large load capacitors . These solutions apply a current buffer in series with C C , sensing and buffering the output AC signal fed back to the input stage.…”

Section: Introductionmentioning

confidence: 99%

“…Advanced frequency compensation schemes rely on single compensation capacitance (C C ) in the form of cascode Miller compensation, enhancing the amplifier's performance, especially for ultra-large load capacitors. [26][27][28][29][30][31] These solutions apply a current buffer in series with C C , sensing and buffering the output AC signal fed back to the input stage. Among the most important solutions based on cascode Miller compensation are crossfeedforward cascode compensation (CFCC) 30 and cascode local impedance attenuation (CLIA), 31 which are explained and analyzed briefly in Appendix A.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Global impedance attenuation network for multistage OTAs driving a broad range of load capacitor

Valinezhad

Grasso

2020

Circuit Theory & Apps

Self Cite

Summary Advanced multistage amplifiers suffer from load‐dependent stability issues, which limit the load capacitor range they can drive. In this work, the concept of global impedance attenuation (GIA) network is introduced to improve an amplifier's stability in the presence of significant load capacitor variations. Composed of multiple parallel resistor‐capacitor (RC) branches, the equivalent high‐frequency output impedance of gain stages is shaped by the GIA network such that a desired frequency spectrum is obtained over a wide range of load capacitor. The parasitic poles at the output of the gain stages are nullified by the proposed network, thereby simplifying the amplifier's transfer function and reducing the minimum load capacitor it can drive. The idea is applied to design a three‐stage operational transconductance amplifier (OTA) with cascode global impedance attenuation (CGIA). Small‐signal analysis shows that the OTA is stable regardless of the load capacitor, and it can drive very small to ultra‐large load capacitors. This feature is verified by the post‐layout simulations of a CGIA amplifier in 0.18‐μm complementary metal‐oxide semiconductor (CMOS) process. The core occupies a die area of 0.0053 mm2 while consuming a static current of 10.97 μA from 1.8‐V voltage supply. The unity‐feedback configuration is unconditionally stable for any load capacitor higher than 10 pF. To the best of our knowledge, this corresponds to the widest range of load capacitance reported for prior‐art three‐stage amplifiers.

Dual loop cascode‐Miller compensation with damping factor control unit for three‐stage amplifiers driving ultralarge load capacitors

Dashti

2018

Circuit Theory & Apps

Self Cite

An area-efficient amplifier topology is presented for three-stage amplifiers driving ultralarge load capacitor with reduced power consumption. It contains two high-speed ac feedback loops made from embedded current buffers and smallsize compensation capacitors, which pushes the nondominant complex poles to very high frequencies. To further improve the stability, a local impedance damping block is embedded. At the higher frequencies, it suppresses the high resistive property at the second-stage output, thereby increasing the damping factor of the complex poles and improving the overall gain margin. For identical bandwidth, the overall silicon area of the on-chip compensation capacitor is therefore decreased, leading to enhanced small-signal and large-signal performance metrics. Coined dual loop cascode-Miller compensation with damping factor control unit, the effectiveness of the proposed approach is investigated through simulation results in 90-nm complementary metal-oxide-semiconductor (CMOS) technology. An implementation based on the proposed technique consumes a quiescent current of 17 μA from a 1.2 V voltage supply. For a load capacitance equal to 560 pF, it achieves a gain-bandwidth frequency of 4.34 MHz, an average slew-rate of 1.72 V/μs, and an average settling time of 0.52 μs, when the overall compensation capacitance is set to 1.55 pF. The proposed design can supply the load capacitors up to 35 nF.