Single multiplexed assays could replace the standard 2-tiered (STT) algorithm recommended for the laboratory diagnosis of Lyme disease if they perform with a specificity and a sensitivity superior or equal to those of the STT algorithm. We used human serum rigorously characterized to be sera from patients with acute- and convalescent-phase early Lyme disease, Lyme arthritis, and posttreatment Lyme disease syndrome, as well as the necessary controls (n = 241 samples), to select the best of 12 Borrelia burgdorferi proteins to improve our microfluidic assay (mChip-Ld). We then evaluated its serodiagnostic performance in comparison to that of a first-tier enzyme immunoassay and the STT algorithm. We observed that more antigens became positive as Lyme disease progressed from early to late stages. We selected three antigens (3Ag) to include in the mChip-Ld: VlsE and a proprietary synthetic 33-mer peptide (PepVF) to capture sensitivity in all disease stages and OspC for early Lyme disease. With the specificity set at 95%, the sensitivity of the mChip-Ld with 3Ag ranged from 80% (95% confidence interval [CI], 56% to 94%) and 85% (95% CI, 74% to 96%) for two panels of serum from patients with early Lyme disease and was 100% (95% CI, 83% to 100%) for serum from patients with Lyme arthritis; the STT algorithm detected early Lyme disease in the same two panels of serum from patients with early Lyme disease with a sensitivity of 48.5% and 75% and Lyme arthritis in serum from patients with Lyme arthritis with a sensitivity of 100%, and the specificity was 97.5% to 100%. The mChip-Ld platform outperformed the STT algorithm according to sensitivity. These results open the door for the development of a single, rapid, multiplexed diagnostic test for point-of-care use that can be designed to identify the Lyme disease stage.

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In this paper we present an analytical experimental study regarding the extraction and analysis of 28 nm FD-SOI MOSFET parameters, from room temperature down to 25 K, and from micro-to nanometer gate lengths. It is shown that the FD-SOI device behavior with temperature can reliably be described by the already established theory of physics for deep cryogenic conditions: Boltzmann statistics and phonon scattering mechanisms are the two main factors that define the device electrical behavior. Moreover, we also demonstrate the advantage of the Y-function as a parameter extraction method, across different channel lengths, and a wide temperature range. We demonstrate the dependence of threshold voltage, subthreshold swing, low-field mobility and source-drain series resistance on temperature, and how this may be affected by the gate length decrease.

A comprehensive Kubo-Greenwood modelling of FDSOI MOS devices is performed down to deep cryogenic temperatures. It is found that a single set of mobility parameters is only necessary to fit the capacitance and drain current transfer characteristics versus temperature for long channel devices. In contrast, in short channel transistors, the neutral scattering mobility component µN is found to decrease at small gate length due to the increased impact of neutral defects close to source/drain ends whatever the temperature. Moreover, a closed-form analytical expression for the Coulomb scattering has been developed, useful for device compact modelling.

This work studies self-heating effects in InGaAs cryogenic HEMT devices, which aim at the enhancement of control/readout electronics performance in quantum computers. Starting from the well-known method of gate resistance thermometry, documented in literature for its reliable results, we characterized these devices down to deep cryogenic temperatures, namely 10 K, typical of signal-processing electronics for qubits, such as low-noise amplifiers (LNA). We furthermore compared the results with those belonging to far more industrialized silicon technologies (Si FDSOI and bulk), showing exceptional performance of the InGaAs HEMTs thanks to their quantum well structure, which combined with their high electron-mobility, makes them a great study case for the technologies of the future.

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This work presents a detailed electrical characterization of planar InGaAs on Insulator MOSFETs from room temperature (namely 300 K) down to deep cryogenic temperatures (10 K). The main electrical parameters of MOSFET operation (threshold voltage Vt, low-field mobility μ0, and subthreshold swing, SS) were extracted in both linear and saturation regions of operation through the consolidated Y-function method, for gate lengths down to 10 nm. The extracted parameters are first analyzed versus temperature and length and then compared against a more mature technology such as Silicon FDSOI MOSFETs. The results reveal competing advantages of the III-V alloy, particularly when going down to cryogenic temperatures.

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