Low temperature behavior of FD-SOI MOSFETs from micro- to nano-meter channel lengths

Abstract

In this paper we present an analytical experimental study regarding the extraction and analysis of 28 nm FD-SOI MOSFET parameters, from room temperature down to 25 K, and from micro-to nanometer gate lengths. It is shown that the FD-SOI device behavior with temperature can reliably be described by the already established theory of physics for deep cryogenic conditions: Boltzmann statistics and phonon scattering mechanisms are the two main factors that define the device electrical behavior. Moreover, we also demonstrate the advantage of the Y-function as a parameter extraction method, across different channel lengths, and a wide temperature range. We demonstrate the dependence of threshold voltage, subthreshold swing, low-field mobility and source-drain series resistance on temperature, and how this may be affected by the gate length decrease.

Temperature-Dependent Narrow Width Effects of 28-nm CMOS Transistors for Cold Electronics

“…Several reports have investigated cryogenic characteristics and modeling of bulk MOSFETs, [14]- [22] FinFETs, [12]- [23], and fully-depleted silicon-oninsulator (SOI) FETs [23]- [27] with L G ranging from 0.35 µm to 14 nm. However, NWEs on advanced CMOSFETs operating at cryogenic temperatures remain to be addressed.…”