Lambert-W function-based parameter extraction for FDSOI MOSFETs down to deep cryogenic temperatures

Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature

“…This improvement is similar to reported long channel devices on bulk Si and FD SOI [24]- [26], and larger than the result reported in Ref. [24], [25], [27] with similar gate length (∼60 nm) implying a significant improvement in the mobility with reducing temperature in GAA Si NW p-FET. As mentioned above, The IIS process has the advantage of less defects at the source (drain)/channel junctions created by ion implantation.…”

“…Furthermore, a high G m of ∼204 μS/μm at V d = −0.1 V is obtained at 5.5 K, which is 3 times larger compared to G m (∼69 μS/μm) at RT as shown in Fig.4a. This improvement is similar to reported long channel devices on bulk Si and FD SOI[24]-[26], and larger than the result reported in Ref [24],[25],[27]. with similar gate length (∼60 nm) implying a significant improvement in the mobility with reducing temperature in GAA Si NW p-FET.…”

“…As mentioned above, The IIS process has the advantage of less defects at the source (drain)/channel junctions created by ion implantation. Therefore, few neutral defects are induced in the channel leading to negligible neutral defect scattering and thus the improved G m and mobility at Cryo-Ts[27].Fig. 4a also plots the extracted V th as a function of temperature.…”

Detailed electrical characterization of 200 mm CMOS compatible GaN/Si HEMTs down to deep cryogenic temperatures

“…It clearly appears that the low field mobility for short channel is much less temperature dependent than for long channels, revealing a clear change in scattering mechanism as reducing the gate length. Indeed, in long channels, µ 0 is likely dominated by phonon scattering explaining the mobility increase at lower T. Instead, in short channels, µ 0 is almost constant with temperature, which is indicative of neutral scattering domination as was observed in scaled Si MOSFETs [19]. Therefore, these low field mobility data versus temperature and gate length were tentatively modelled using the same approach employed in Si MOSFET, where the mobility can be described as [19],…”

“…where C ox is the maximum gate-to-channel capacitance associated to the coupling capacitance between the metal gate and GaN 2DEG through the AlGaN layer, µ 0 is the low field mobility and V th the threshold voltage. The source-drain series resistance R sd is then extracted, in linear operation, from the plateau of the quantity defined below plotted in strong inversion, On the other hand, the transistor parameter extraction was performed using the Lambert-W function modelling approach developed for Si MOS transistors at 300K [18] and recently extended at cryogenic temperatures [19]. In this case, the drain current in linear region including the R sd influence is given by,…”