Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature

Abstract

Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW diameter of 5 nm are fabricated and characterized from room temperature (RT) down to 5.5 K. Thanks to the improved electrostatics by the scaled NW and 3D GAA structure, close to ideal transfer characteristics are obtained at both RT and 5.5 K with a sharp switching. Benefiting from less defects in Si created by the implantation into silicide (IIS) process, the band tail effects and neutral defects scattering are suppressed. Therefore, the fabricated Si GAA NW p-FETs provide very low subthreshold swing SS of 3.4 mV/dec in the weak inversion region and an average SS th of 14 mV/dec measured from the off-state to the threshold voltage, as well as an improved transconductance G m at 5.5 K.

Toward Low‐Power Cryogenic Metal‐Oxide Semiconductor Field‐Effect Transistors

“…b) Cross section of a gate-all-around silicon nanowire FET with a gate length L ¼ 70 nm and 4 nm HfO 2 gate dielectric. [45] 10 -11 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 I d (A/μm) temperatures, the threshold voltage needs to be such that in the off-state the channel represents a potential barrier with a very small height in the few meV range (as illustrated in Figure 1a). Since tunneling depends exponentially on the potential barrier height, cCMOS devices are much more affected by source-drain tunneling as compared to room temperature.…”

“…b) Cross section of a gate‐all‐around silicon nanowire FET with a gate length and 4 nm gate dielectric. [ 45 ]…”

“…The lower panel shows a schematic cross section of the device. b) Cross section of a gate-all-around silicon nanowire FET with a gate length L ¼ 70 nm and 4 nm HfO 2 gate dielectric [45].…”

Investigation of the mechanical and transport properties of InGeX3 (X = S, Se and Te) monolayers using density functional theory and machine learning

“…In recent years, CMOS (complementary metal oxide semiconductor) integrated circuits based on silicon have been developed rapidly, due to which transistor's size has entered the 5 nm node, and has become close to the physical limit. [1][2][3][4] Due to the size effect, it is diffficult to follow Moore's Law. 5 To keep the device performance unchanged, the processing of the transistors has been significantly improved.…”

Comparative Cryogenic Investigation of FD-SOI Devices with Doped Epitaxial and Metallic Source/Drain

“…According to the literature, the saturation of the critical parameters occurs due to defects and interface traps induced by the source/drain implantation, which play a key role in the band tail effect at deep cryogenic temperatures and prevent the theoretically predicted performance enhancement of the PMOS device. [12][13][14][15][16] It has been shown that SiGe epitaxy can improve the drain current and mobility of FD-SOI devices by introducing strain at cryogenic temperatures. 14,17 In addition, the utilization of a silicide metallic source/drain results in dopant segregation through the implantation into the silicide (Silicide As Diffusion Source, SADS).…”