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The quest for mass storage and the diversity of end-user applications led to an aggressive scaling of the NAND Flash memory. A key factor to its success is the high density integration potential, which allows fabrication of large memory arrays. Reduction of the feature size below 40 nm may, however, require modifications of the conventional floating gate cell architecture, due to lack of physical space between neighboring cells, which no longer allows wrapping of the control gate over the floating gate. This has consequences on both intra- as well as inter-cell levels, calling for the introduction of high-k dielectrics in Flash memory. In this paper, we take a top-down stance and translate device characteristics into material requirements and/or points of attention that need to be addressed in order to ensure a successful continued scaling of the Flash memory for the upcoming technology generations.

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