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A fully analytical potential model, valid in the weak inversion regime of short-channel cylindrical gate-all-around (GAA) MOSFET, is proposed. The model derivation is based on a previous analytical expression for tetragonal GAA MOSFET and the rotational symmetry of the tetragonal cross section. Device simulations were performed to verify that the potential distribution along the channel is properly described in all positions within the silicon body. Using the potential model, analytical expressions for the threshold voltage, subthreshold swing and drain-induced barrier lowering have been derived. Including the short-channel effects within an existing model for the subthreshold leakage current and an analytical drain current model of long-channel devices in strong inversion, a compact drain current model has been derived describing with good accuracy the transfer and output characteristics of short-channel GAA MOSFETs in all regions of operation.

A model for the grain-boundary barrier height of undoped polycrystalline silicon thin-film transistors is developed based on a rodlike structure of the grains with a square cross section and a Gaussian energy distribution of the trapping states at the grain boundaries. An analytical expression for the threshold voltage is derived in terms of the distribution parameters of the grain-boundary trapping states, the grain size, and the gate oxide thickness. Comparison between the developed model and the experimental drain current versus gate voltage data has been made and excellent agreement was obtained. The key parameters affecting the threshold voltage and the channel conductance of the transistor were investigated by computer stimulation. The threshold voltage is mainly affected by the grain size and the gate oxide thickness. For the improvement of the channel conductance, besides the passivation of the grain-boundary trapping states, the increase of the grain size and mainly the scaling down of the gate oxide thickness are the key factors.

The low frequency noise technique is used to obtain the volume profile of traps in the SiNx gate dielectric of hydrogenated amorphous silicon (a-Si:H) and nanocrystalline silicon (nc-Si:H) thin film transistors (TFTs). In both a-Si:H and nc-Si:H TFTs, within the range of probing depth in the gate dielectric, the traps have a uniform spatial distribution which is consistent with the observed pure 1/f noise. The experimental results show that the gate dielectric trap properties near the interface are dependent on the channel material with the trap density in nc-Si:H TFTs being much smaller in comparison with the a-Si:H TFTs.

The field-effect conductance activation energy Ea as a function of the gate voltage Vg is investigated for polycrystalline silicon thin-film transistors. An analytical expression for Ea is obtained for various models of the bulk and interface states. Using a computer minimization program to fit the experimental Ea vs Vg data with the theory, the energy distribution of the bulk states and the interface states are separated for nonhydrogenated and hydrogenated polycrystalline silicon thin-film transistors. In both cases, the bulk states have exponential band tails and a wide peak near the midgap and the interface states have an exponential distribution from the band edge.

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Articles you may be interested inElectrical transport through heterojunctions of single-walled carbon/silicon carbide/carbon nanotubes Electrical conduction and electroluminescence in nanocrystalline silicon-based light emitting devices Band offsets and transport mechanisms of hydrogenated nanocrystalline silicon/crystalline silicon heterojunction diode: Key properties for device applications Nanocrystalline carbon ͑nc-C͒ films were grown by magnetron sputtering on n-type Si substrates at room temperature and at substrate bias voltage Ϫ200 V. The electrical transport properties of nc-C/n-Si heterojunctions are investigated by current-voltage measurements at various temperatures and capacitance-voltage measurements at room temperature. The results indicate that the forward conduction is determined by thermionic emission over a potential barrier of height 0.3 eV at temperatures above 180 K. At lower temperatures and low currents, multistep tunneling current dominates. At low reverse voltages, the reverse conduction is dominated by current generated within the depletion region, while at higher voltages the current is due to Poole-Frenkel emission.