Determination of bulk states and interface states distributions in polycrystalline silicon thin-film transistors

Dimitriadis, C. A.; Tassis, D. H.; Economou, N. A.; Lowe, A.

doi:10.1063/1.354648

Cited by 65 publications

(25 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…7 we can see there is good agreement on both linear and logarithmic scales. This result was found by setting , cm , which is in agreement with the experimentally measured values in [14] and giving the silicon regions a reduced mobility of cm V s. Capture rates and source and drain doping were as given in Table I. …”

Section: Comparison With Experimentssupporting

confidence: 79%

Improved Off-Current and Subthreshold Slope in Aggressively Scaled Poly-Si TFTs With a Single Grain Boundary in the Channel

Walker

Mizuta

Uno

et al. 2004

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Abstract-A polycrystalline-silicon thin-film transistor (TFT), with a single grain boundary (GB) present in the channel, is simulated using two-dimensional numerical simulation, which includes a model of deep trap states at GBs. It is observed that the potential barrier resulting from a GB in the channel acts to suppress current flowing through the channel when the barrier height is greater than the thermal voltage. The conduction mechanism in the subthreshold regime is clarified. The turn-on characteristics of the device are controlled primarily by gate-induced grain barrier lowering as opposed to modulation of carriers in the channel by the gate voltage. In the negative bias region it is found that suppression of the off current is aided by the GB potential barrier. Scaling of the various geometrical parameters of the device are investigated. Improved subthreshold characteristics, compared to an equivalent silicon-on-insulator (SOI) structure, are found for aggressively scaled devices, due to the presence of a GB in the channel.

show abstract

Section: Comparison With Experimentssupporting

confidence: 79%

Improved Off-Current and Subthreshold Slope in Aggressively Scaled Poly-Si TFTs With a Single Grain Boundary in the Channel

Walker

Mizuta

Uno

et al. 2004

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

show abstract

“…In addition, (7) shows that n t follows the MN rule and allows the calculation of n t from E A and S IDS /I gives N' Tmax ≥10 17 cm -3 eV -1 . This value is convenient with previous published results [14].…”

Section: Then It Can Be Expressed Assupporting

confidence: 74%

Thermal dependence of low-frequency noise in polysilicon thin film transistors

2009

View full text Add to dashboard Cite

Thermal dependence of low frequency noise in low temperature (600°C) polysilicon thin film transistors is studied in devices biased from weak to moderate inversion and operating in the linear mode. Drain current noise spectral density, measured in the temperature range from 260K to 310K, is thermally activated following the Meyer Neldel rule. Analysis of the thermal activation of noise, supported by the theory of trapping/detrapping processes of carriers into oxide traps located close to the interface, leads to the calculation of the deep state interface distribution in function of the Meyer Neldel characteristic energy.

show abstract

“…The values chosen are in the range suggested in ref. 27 and are shown in Table I. 3. Simulation of a 400 nm TFT 3.1 Device structure Figure 2 shows the basic device structure we used in the device modelling.…”

Section: Trap State Distribution Modelmentioning

confidence: 99%

“…[20][21][22] or as Gaussian terms used in refs. [26][27][28]. We chose to use Gaussian terms because the studies dealing with SPC films suggest a peak in trap states near the mid gap and we are considering SPC films in this work.…”

Section: Trap State Distribution Modelmentioning

confidence: 99%

Simulation Study of the Dependence of Submicron Polysilicon Thin-Film Transistor Output Characteristics on Grain Boundary Position

Walker

Uno

Mizuta

2005

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

We investigate the impact of varying the grain boundary (GB) position on the output (I d -V d ) characteristics of submicron single GB polysilicon thin film transistors (TFTs), by two-dimensional (2D), drift-diffusion based, device simulation. We employ a localized GB trapping model with a distribution of both donor-like and acceptor-like trap states over the forbidden energy gap of the GB region. We show that for devices with channel lengths in the deep submicron regime, significant variations in output conductance (g d ) occur as the GB position is varied. Specifically, we find that output conductance increases as the GB approaches the drain edge. Furthermore, the sensitivity of output conductance to the GB position increases as channel length decreases. The findings have important implications for any future analogue three-dimensional (3D) IC design that uses polysilicon as a device material.

show abstract

Determination of bulk states and interface states distributions in polycrystalline silicon thin-film transistors

Cited by 65 publications

References 25 publications

Improved Off-Current and Subthreshold Slope in Aggressively Scaled Poly-Si TFTs With a Single Grain Boundary in the Channel

Improved Off-Current and Subthreshold Slope in Aggressively Scaled Poly-Si TFTs With a Single Grain Boundary in the Channel

Thermal dependence of low-frequency noise in polysilicon thin film transistors

Simulation Study of the Dependence of Submicron Polysilicon Thin-Film Transistor Output Characteristics on Grain Boundary Position

Contact Info

Product

Resources

About