Improved Off-Current and Subthreshold Slope in Aggressively Scaled Poly-Si TFTs With a Single Grain Boundary in the Channel

Abstract

Abstract-A polycrystalline-silicon thin-film transistor (TFT), with a single grain boundary (GB) present in the channel, is simulated using two-dimensional numerical simulation, which includes a model of deep trap states at GBs. It is observed that the potential barrier resulting from a GB in the channel acts to suppress current flowing through the channel when the barrier height is greater than the thermal voltage. The conduction mechanism in the subthreshold regime is clarified. The turn-on characteristics of the device are controlled primarily by gate-induced grain barrier lowering as opposed to modulation of carriers in the channel by the gate voltage. In the negative bias region it is found that suppression of the off current is aided by the GB potential barrier. Scaling of the various geometrical parameters of the device are investigated. Improved subthreshold characteristics, compared to an equivalent silicon-on-insulator (SOI) structure, are found for aggressively scaled devices, due to the presence of a GB in the channel.

Simulation Study of the Dependence of Submicron Polysilicon Thin-Film Transistor Output Characteristics on Grain Boundary Position

“…The need to lower the GB potential barrier is the cause of an increase in threshold voltage, relative to an equivalent SOI device. 18) In terms of the carrier concentration of the inversion layer, the TFT will have a lower number of carriers than an SOI equivalent device under the same gate bias. To illustrate the reduced concentration of carriers in the inversion layer, in Fig.…”

Thin-Film Bipolar Transistors on Recrystallized Polycrystalline Silicon Without Impurity Doped Junctions: Proposal and Investigation

“…As the TFTs are scaled down to the nano-scale regime, channel length of the TFTs approaches the grain size and it is possible to have a single GB in the re-crystallized silicon film. However, controlling the location of the single GB in the device is difficult [9], [16]. Contact resistances are considered to be zero at all the contacts.…”

“…L OW temperature polycrystalline silicon (Poly-Si) thin-film transistors (TFTs) on insulating substrates such as glass and plastics, even at sub-100 nm channel lengths, are aggressively investigated in the literature [1]- [9]. The use of low thermal budget ( 600 C), and less expensive substrate materials such as plastic and glass makes TFTs a low-cost choice for a wide range of applications such as active matrix liquid crystal displays (AMLCDs) [1], and memory devices [2].…”

Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture

“…Previously published simulation studies of the effect of Fermi-level pinning at poly-Si grain boundaries have centered on 2-D simulations [23] or 3-D simulations with only a single grain boundary [16], [28]. First, we have studied the case when only one grain boundary crosses the middle of the channel parallel to the source/drain junctions.…”