Simulation Study of the Dependence of Submicron Polysilicon Thin-Film Transistor Output Characteristics on Grain Boundary Position

Abstract

We investigate the impact of varying the grain boundary (GB) position on the output (I d -V d ) characteristics of submicron single GB polysilicon thin film transistors (TFTs), by two-dimensional (2D), drift-diffusion based, device simulation. We employ a localized GB trapping model with a distribution of both donor-like and acceptor-like trap states over the forbidden energy gap of the GB region. We show that for devices with channel lengths in the deep submicron regime, significant variations in output conductance (g d ) occur as the GB position is varied. Specifically, we find that output conductance increases as the GB approaches the drain edge. Furthermore, the sensitivity of output conductance to the GB position increases as channel length decreases. The findings have important implications for any future analogue three-dimensional (3D) IC design that uses polysilicon as a device material.

Thin-Film Bipolar Transistors on Recrystallized Polycrystalline Silicon Without Impurity Doped Junctions: Proposal and Investigation

“…To overcome the above problems, in this paper, we demonstrate the possibility of making bipolar transistors on intrinsic recrystallized polycrystalline thin-film silicon without the need for impurity diffusion. Using two-dimensional simulations, similar to that of Walker's approach [16]- [23] for TFTs, we demonstrate the possibility of realizing a polysilicon Bipolar Charge Plasma Transistor (poly-Si BCPT). The proposed device could be suitable for different applications such as the driver circuits of the displays.…”

“…To account for the impact ionization, Selberherr's model is invoked [34]. We have calibrated our models by first reproducing the results for a short channel TFT with a single grain boundary in the channel region as given in [16]. As the TFTs are scaled down to the nano-scale regime, channel length of the TFTs approaches the grain size and it is possible to have a single GB in the re-crystallized silicon film.…”

“…As the TFTs are scaled down to the nano-scale regime, channel length of the TFTs approaches the grain size and it is possible to have a single GB in the re-crystallized silicon film. However, controlling the location of the single GB in the device is difficult [9], [16]. Contact resistances are considered to be zero at all the contacts.…”

“…In our model, trap states are located only in the grain boundary (GB) region. We have considered a 4 nm long GB in the base region of the poly-Si BCPT just as in the case of the poly-Si TFT [16], [35]. As is done in Walker's approach [16], we have assumed the GB to be oriented perpendicular to the semiconductor surface for its maximum impact on carrier transport, although, in a real film the GB orientation would be random.…”

CdS Thin Film Transistor for Inverter and Operational Amplifier Circuit Applications

“…The corresponding computation time is also excessive. Prior work in the literature, in the area of polycrystalline silicon, indicates simulations would be possible with as little as one grain boundary taken along FET channel [48].…”