Thermal dependence of low-frequency noise in polysilicon thin film transistors

Pichon, Laurent; Cretu, Bogdan; Boukhenoufa, Abdelmalek

doi:10.1016/j.tsf.2009.02.055

Cited by 10 publications

(6 citation statements)

References 11 publications

(16 reference statements)

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“…Third, the lowfrequency noise in MOS transistors is higher than the noise in BJTs, as one can see in Figure 15. In this figure, the data are for 134 nMOS transistors from [22,47,48,49,50,51,72,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123], and for 53 pMOS transistors from [47,52,86,…”

Section: Noise In Mos Transistorsmentioning

confidence: 99%

“…Input-referred voltage noise S V G (gate voltage 1/f noise at 1Hz) in silicon MOS transistors compared to the corresponding S V B in silicon npn BJTs. ( ) for nMOS transistors from[22,47,48,49,50,51,72,82,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123], ( ) for pMOS transistors from[47,52,…”

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Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

2022

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Section: Noise In Mos Transistorsmentioning

confidence: 99%

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Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

2022

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“…By considering the tunneling theory of carriers into the gate oxide traps located close to the interface and the following trapping/de-trapping processes, the corresponding localized states distribution N T can be expressed by 10,20 :…”

Section: Analysis Of Low Frequency Noise Characteristics In P-type Pomentioning

confidence: 99%

Analysis of low frequency noise characteristics inp-type polycrystalline silicon thin film transistors

Liu

Fang

2017

Mod. Phys. Lett. B

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Low frequency noises in the p-type polycrystalline silicon thin film transistors are investigated. It shows a pure 1/f γ (with γ near one) noise behavior which can be explained by emission and trapping processes of carriers between trapping states. Subsequently, the gate voltage-dependent drain current noise power spectral densities closely follow the mobility fluctuation model, and the average Hooge's parameter is then extracted. By considering traditional tunneling processes, the flat-band voltage spectral density is extracted and the concentration of traps in the grain boundary is calculated to be 7.17×10 20 cm −3 eV −1 . By converting the frequency to tunneling depth of carriers in the gate oxide, the spatial distribution of gate oxide trapped charges are obtained. Finally, the distribution of localized states in the energy band is extracted. The experimental results show an exponential deep states and tail states distribution in the band gap while N DD is about 1.5 × 10 20 cm −3 eV −1 , T DD is ∼ 617 K, N TD is ∼ 3.6 × 10 21 cm −3 eV −1 and T TD is ∼ 265 K.

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“…Previous experimental studies 17,18 reported that the static drain current I DS and the 1 / f noise drain current spectral S IDS , for TFTs biased from weak to strong inversion ͑i.e., from sub-to above-threshold region͒, are thermally activated both following the empirical MN rule 8 according to…”

Section: A Temperature Dependencementioning

confidence: 99%

Improvement in the determination by 1/f noise measurements of the interface state distribution in polysilicon thin film transistors in relation with the compensation law of Meyer Neldel

Pichon

Boukhenoufa

Cretu

et al. 2009

Journal of Applied Physics

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Erratum: "Effect of excimer laser annealing on the structural and electrical properties of polycrystalline silicon thin-film transistors" [J.Electrical and noise properties of thin-film transistors on very thin excimer laser annealed polycrystalline silicon films Appl.Low-frequency ͑1 / f͒ noise is studied in N-channel furnace solid phase crystallized ͑FSPC͒ and in laser solid phase crystallized ͑LSPC͒ polysilicon thin film transistors ͑TFTs͒ biased from weak to strong inversion. Noise analysis is supported by the theory of charge carrier trapping/detrapping at the interface tunneling into gate oxide traps. The distribution of interface trap states ͑N T ͒ is deduced from the number of carriers trapped into the oxide. Noise measurements for devices biased from weak to moderate inversion allow the determination of the distribution of deep level trap states associated with dangling bond-type defects ͑N Tdb ͒, whereas measurements from moderate to strong inversion give the distribution of shallow level trap states ͑N Tts ͒ associated with strained bond defects. The noise analysis clearly shows that the slope of both exponential distributions equals to the reverse of the Meyer Neldel energy E MN ͑0.035 and 0.055 eV for FSPC and LSPC TFTs, respectively͒. For LSPC devices the resulting distribution of interface states ͑N T = N Tdb + N Tts ͒ is one decade lower and it is attributed to the effects of the laser annealing on the active layer crystal quality.

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Thermal dependence of low-frequency noise in polysilicon thin film transistors

Cited by 10 publications

References 11 publications

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

Analysis of low frequency noise characteristics inp-type polycrystalline silicon thin film transistors

Improvement in the determination by 1/f noise measurements of the interface state distribution in polysilicon thin film transistors in relation with the compensation law of Meyer Neldel

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