Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs

Fasarakis, N.; Tsormpatzoglou, A.; Tassis, D. H.; Pappas, Ilias O.; Papathanasiou, K.; Bucher, Matthias; Ghibaudo, G.; Dimitriadis, C. A.

doi:10.1109/ted.2012.2195318

Cited by 49 publications

(30 citation statements)

References 35 publications

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“…(3) by numerical iteration. This special function is commonly used in MOSFET modeling [25][26][27] and in electronics. 28 Equation (3) can be written in the general form of ln…”

Section: Analytical Drain Current Modelmentioning

confidence: 99%

Analytical surface-potential-based drain current model for amorphous InGaZnO thin film transistors

Tsormpatzoglou

Hastas

Choi

et al. 2013

Journal of Applied Physics

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A fully analytical surface-potential-based drain current model for amorphous InGaZnO (α-IGZO) thin film transistors (TFTs) has been developed based on a Gaussian distribution of subgap states, with the central energy fixed at the conduction band edge, which is approximated by two exponential distributions. This model includes both drift and diffusion components to describe the drain current in all regions of operation. Using an empirical mobility relationship that depends on both horizontal and vertical electric field, it is demonstrated that the model describes accurately the experimental transfer and output characteristics, making the model suitable for the design of circuits using α-IGZO TFTs.

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“…(3) by numerical iteration. This special function is commonly used in MOSFET modeling [25][26][27] and in electronics. 28 Equation (3) can be written in the general form of ln…”

Section: Analytical Drain Current Modelmentioning

confidence: 99%

Analytical surface-potential-based drain current model for amorphous InGaZnO thin film transistors

Tsormpatzoglou

Hastas

Choi

et al. 2013

Journal of Applied Physics

Self Cite

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“…The total gate or channel charge Q g is obtained by integrating the mobile charge sheet density Q i over the channel length L, i.e., where W eff = 2H fin + W fin is the effective channel width. The charge sheet density Q i (y) is given by [18] …”

Section: A Gate Chargementioning

confidence: 99%

“…Whereas several analytical approaches have been developed for the calculation of the potential distribution within the channel [7]- [11], most of the published work on drain current modeling in short-or long-channel FinFETs is limited to double-gate (DG) devices [12]- [16]. Recently, we have proposed a compact and analytical drain current model suitable to nanoscale DG and TG FinFETs [17], [18]. However, this drain current model has to be completed with a compact capacitance-voltage (C-(V ) model, to Manuscript make it suitable for implementation in a SPICE simulator for circuit design and performance exploitation.…”

Section: Introductionmentioning

confidence: 99%

Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs

Fasarakis

Tsormpatzoglou

Tassis

et al. 2012

IEEE Trans. Electron Devices

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A charge-based compact capacitance model has been developed describing the capacitance-voltage characteristics of undoped or lightly doped ultra-scaled triple-gate fin field-effect transistors. Based on a unified expression for the drain current and the inversion sheet charge density, i.e., the Ward-Dutton linear-charge-partition method and the drain current continuity principle, all trans-capacitances are analytically derived. The developed capacitance model is valid in all regions of operation, from the subthreshold region to the strong inversion region and from the linear region to the saturation region. The gate and source transcapacitances have been validated by 3-D numerical simulations over a large range of device dimensions. The parameters of the capacitance model can be used to accurately predict the transfer and output characteristics of the transistors, making this compact model very useful for circuit designers.

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“…In recent years, the high-κ / metal gate (HKMG) devices with vertical channel, i.e., the fin-typed field-effect-transistors (FinFETs) are playing an important role in semiconductor industry and have been investigated widely due to their good controllability of channel compared to planar MOSFET [2][3][4][5]. However, with device scaling, various randomness effects resulting from the random nature of manufacturing process have induced significant fluctuations on electrical characteristics [6].…”

Section: Introductionmentioning

confidence: 99%

“…In addition, the metal gate may result in the third random fluctuation source, so-called the work function fluctuation (WKF) [9] owing to the dependency of work function on metal grain's orientation. Many studies concerning individual or pair-wised fluctuation sources have been reported [1,[3][4][5][6][7][8][9][10][11][12][13][14] for SOI and Bulk FinFETs. Unfortunately, the simultaneous comparison of these random fluctuation sources for n-and p-type HKMG bulk FinFETs have not been explored yet…”

Section: Introductionmentioning

confidence: 99%

Statistical device simulation of intrinsic parameter fluctuation in 16-nm-gate n- and p-type Bulk FinFETs

Chen¹,

Huang²,

Hsu³

et al. 2013

2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013)

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In this paper, we estimate the influence of random dopants (RDs), interface traps (ITs), and random work functions (WKs) using the experimentally calibrated 3D device simulation on DC characteristic of high-κ / metal gate n-and p-type bulk fin-typed field-effect-transistors. We further study these intrinsic parameter fluctuations' impact on drain induced barrier lowering (DIBL). The main findings of this work show the RDF and WKF on n-type device are larger than that of p-type one. The DIBL is dominated by the number of random dopants.978-1-4799-0676-5/13/$31.00 ©2013 IEEE

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Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs

Cited by 49 publications

References 35 publications

Analytical surface-potential-based drain current model for amorphous InGaZnO thin film transistors

Analytical surface-potential-based drain current model for amorphous InGaZnO thin film transistors

Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs

Statistical device simulation of intrinsic parameter fluctuation in 16-nm-gate n- and p-type Bulk FinFETs

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