Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs

Abstract

A charge-based compact capacitance model has been developed describing the capacitance-voltage characteristics of undoped or lightly doped ultra-scaled triple-gate fin field-effect transistors. Based on a unified expression for the drain current and the inversion sheet charge density, i.e., the Ward-Dutton linear-charge-partition method and the drain current continuity principle, all trans-capacitances are analytically derived. The developed capacitance model is valid in all regions of operation, from the subthreshold region to the strong inversion region and from the linear region to the saturation region. The gate and source transcapacitances have been validated by 3-D numerical simulations over a large range of device dimensions. The parameters of the capacitance model can be used to accurately predict the transfer and output characteristics of the transistors, making this compact model very useful for circuit designers.

A software tool for aging analysis of the CMOS inverter based on hot carrier degradation modeling

“…The device model used for the simulations is based on the work published in [6][7][8] for the drain current I ds and the internal trans-capacitances C xy of Triple Gate FinFETs. In order to execute the algorithm flow of the proposed tool, the FinFET device model is implemented in Matlab.…”

“…The device [6][7][8] and HC degradation models [3,4] along with the algorithm that implements the reliability analysis are coded in Matlab.…”

RF modeling of 40‐nm SOI triple‐gate FinFET

“…Several dc and RF models have been proposed in the literature , as well as the so‐called artificial neural network approach . However, full compact models, which describe the FinFET static and dynamic behaviors, are still needed for analog design.…”

Effects of fin width on high‐ κ /metal gate bulk FinFET devices

“…Introduction: Fin field-effect transistors (FinFETs) are candidates for the sub-22 nm technology node because of the well-suppressed shortchannel effects (SCEs), high transcondutance and an ideal subthreshold swing [1][2][3]. To further reduce SCEs and improve gate control, promising device structures, such as FinFETs, have been developed widely [4][5][6]. Recent research on FinFET devices has reported the relationship between the work function and trap function [7], but few reports have discussed the influence of layout parameters such as fin width, fin height and the number of fins on the electrostatic characteristics of devices.…”