The effects of silicon fin width on the electrostatic characteristics of high-κ/metal gate bulk fin field-effect transistor (FinFET) devices are investigated. Six devices with different layout fin widths and lengths are designed and fabricated. A technology computer-aided design (TCAD) simulation model with the proposed devices simplified as an equivalent circuit with three components (C ox , C s and R s) indicates that for a given layout area, a narrower fin width leads to a worse flat band voltage shift and larger variation of gate capacitance due to increased substrate resistance.
The capacitance-voltage electrical characteristics of fin field-effect transistor (FinFET) varactors, which have fins with different taper angles and rounding radiuses, are investigated. By fitting the results of a three-dimensional correction simulation with those of an experimentally fabricated FinFET varactor, the two key factors of process simulations (taper angle θ and rounding radius r) are extracted. It is found that the capacitance of the FinFET varactor changes when the fin cross-sectional profile varies. The examination presented here is useful in the fabrication of FinFETs. It clarifies the fin cross-sectional profile effect on the FinFET varactor capacitance.
The effects of the depletion capacitance of a varactor between fin field-effect transistor (FinFET) and bulk planar devices are investigated. Fabricated NMOS varactors are characterized and studied. The depletion capacitance of an NMOS varactor in FinFETs is lower than that of the conventional bulk planar one. Thus, the NMOS FinFET varactor provides a larger tuning range (about 10.4 times with respect to minimal capacitance) than the bulk planar one (approximately 3.7 times). The simulation results of the proposed three-dimensional (3D) devices with FinFET and bulk planar varactors show that the depletion layer width of the NMOS varactors in FinFETs is more sensitive to the applied gate voltage than the bulk planar one.
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