Statistical device simulation of intrinsic parameter fluctuation in 16-nm-gate n- and p-type Bulk FinFETs

Abstract

In this paper, we estimate the influence of random dopants (RDs), interface traps (ITs), and random work functions (WKs) using the experimentally calibrated 3D device simulation on DC characteristic of high-κ / metal gate n-and p-type bulk fin-typed field-effect-transistors. We further study these intrinsic parameter fluctuations' impact on drain induced barrier lowering (DIBL). The main findings of this work show the RDF and WKF on n-type device are larger than that of p-type one. The DIBL is dominated by the number of random dopants.978-1-4799-0676-5/13/$31.00 ©2013 IEEE

Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps

“…Recent studies reported the density of interface traps ( D it ) resulting from the orientations of the vertical fin channel of FinFETs [ 6 , 17 ]. The effects of RITs on sub-22-nm FinFETs have also been reported and compared between different device structures [ 18 , 19 ]. Unfortunately, the impact of RITs on 16-nm-gate HKMG bulk FinFET devices has not been clearly discussed yet.…”