Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

“…1. The threshold voltage in [19] is defined quantitatively as the gate voltage at which the minimum carrier charge sheet density at the effective conductive path reaches a value Q th adequate to achieve the turn-ON condition. An empirical expression for Q th has been derived in terms of the drain-bias V ds , device geometrical parameters, and effective conductive path parameters to fit the model with simulated results.…”

“…Considering that the work functions of the front and back metal gates are close, in the case where the front-gate oxide is much thinner, the case for the dominance of the front channel is sufficient to explain the experimental results for a wide range of back-gate biases. Furthermore, to derive analytical expression for the threshold voltage, the effective conductive path concept should be accounted for [19]. Thus, for thinner front-gate oxide, the threshold voltage is defined as the gate voltage at which the electron density at the effective conductive path located at a distance x = x c from the front interface is equal to the doping density N A of the silicon body, that is…”

“…Recently, we developed simple analytical models for the threshold voltage and the ideality factor of the front interface for asymmetrical UTBB FD-SOI MOSFETs [19]. In this paper, we have improved our previous model by defining the threshold voltage as the gate voltage when the electron density at the effective conductive path reaches the doping density of the silicon body.…”

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

“…As an important electrical parameter, the threshold voltage of the devices has been studied extensively. Fasarakis et al [11] and Manan et al [12] developed 2-D threshold-voltage models for SOI (silicon-on-insulator) and SON (silicon-on-nothing) MOSFETs, but Ge channel was not involved. Hu et al [13] proposed a model to account for the sub-threshold performance of UTB Ge MOSFETs, but threshold voltage and high-k gate dielectric were not considered.…”

An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

“…14,15 The effects of back-gate bias voltage on the threshold voltage of FD SOI MOSFETs have been studied in detail. [16][17][18][19][20][21] Yang et al 16 have reported a novel SOI technology called fully depleted silicon-on-insulator-with-active substrate (SOIAS) MOSFET structure in which an oxideisolated polysilicon back-gate electrode was formed beneath the channel and back-gate was used to control the threshold voltage of the device. It was concluded that a dynamic threshold voltage control scheme was needed for high performance and low power requirements.…”