Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Abstract

An analytical drain-current compact model for lightly doped short-channel ultrathin-body and box fully depleted silicon-on-insulator MOSFETs with back-gate control is presented. The model includes the effects of drain-induced barrier lowering, channel-length modulation, saturation velocity, mobility degradation, quantum confinement, velocity overshoot, and self-heating. The proposed model has been validated by comparing with the experimental transfer and output characteristics of devices with the channel lengths of 30 and 240 nm and with back bias varying from −3 to +3 V. The good accuracy of the model makes it suitable for implementation in circuit simulation tools. Index Terms-Back-gate control, compact model, fully depleted silicon-on-insulator (FD-SOI) ultrathin-body and box (UTBB) MOSFETs. 0018-9383

Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

“…The exponential dependence of eff on V b is in agreement with the centroid modeling approach of (5) and of [24], verifying that eff is related to the carriers position in the channel. The effective flat-band voltage power spectral density S Vfbeff is not dependent on either the channel length or the back-gate bias, thus it can be calculated using S Vfb eff = q 2 λkT N t,eff f W LC 2 ox,1 (7) where N t,eff is the effective slow oxide trap volumetric density, related the front and back interface trap densities via the coupling factor of (3b) as N t,eff = N t 1 + C 2 21 · N t 2 .…”

Noise and Fluctuations in Fully Depleted Silicon-on-Insulator MOSFETs

“…Following the RTN modeling approach described in 2.1.d, one can build a self-contained defectaware Verilog-A module for time-domain simulations [82], [83]. For the device static response, we can use the model presented in [84], because it is threshold-voltage-based, allowing for a much more straightforward electrostatic trap impact declaration through an approximate relation:…”

“…In our work [82], a random vertical and lateral position is chosen for each trap assuming a uniform distribution in the oxide. Moreover, for the module to be functional under both stationary and non-stationary conditions, ̅ and ̅ are initialized and then re-calculated at every change of voltage bias or temperature (see Figure 42(b)), using Equations (18) and the local inversion charge density Q iyt calculated by the model [84]. This way, this module can be also used for simulating the recoverable part of the Bias Temperature Instabilities (BTI) degradation (as shown in [82]).…”

Radiation-enhanced channel length modulation induced by trapped charges in buried oxide layer

“…Especially, the main transistor has high drain current. Self-heating of main transistor is very serious, which offsets the uptrend of drain current induced by CLM effect [20,21].…”