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Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO 2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient .A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

Extensive investigation of the drain-current low-frequency noise in n-channel MOSFETs issued from a 14-nm fully depleted silicon-on-insulator technology node has been carried out. The results demonstrate that the carrier number fluctuation (CNF) with correlated mobility fluctuations (CMFs) model accurately and continuously describes the 1/ f noise from weak to strong inversion, from linear to saturation, and for all the back-bias conditions. It is shown that using only two parameters, i.e., the effective flat-band voltage spectral density S Vfb,eff and CMF factor eff , the CNF/CMF noise model can predict the transistor 1/ f noise level of all channel dimensions and under any bias conditions. Thus, it can be easily used in SPICE noise modeling for circuit simulations.Index Terms-Low-frequency noise (LFN), UTBB fully depleted silicon-on-insulator (FDSOI) MOSFETs.

The low frequency noise technique is used to obtain the volume profile of traps in the SiNx gate dielectric of hydrogenated amorphous silicon (a-Si:H) and nanocrystalline silicon (nc-Si:H) thin film transistors (TFTs). In both a-Si:H and nc-Si:H TFTs, within the range of probing depth in the gate dielectric, the traps have a uniform spatial distribution which is consistent with the observed pure 1/f noise. The experimental results show that the gate dielectric trap properties near the interface are dependent on the channel material with the trap density in nc-Si:H TFTs being much smaller in comparison with the a-Si:H TFTs.

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