Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

Abstract

Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO 2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient .A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

“…This behavior cannot be interpreted using constant Coulomb scattering coefficients α sc1,2 occurring in (2) and (3). Based on the carrier centroid dependence of α sc1,2 as in [22] and combining both the remote Coulomb scattering for each interface, we propose to generalize the CMF coefficients under Average drain-current noise versus frequency for nMOS (W/L) = (1/0.08) μm and for different drain and front-gate voltage bias but for a constant drain current ∼50 μA. The back-gate voltage was grounded.…”

Noise and Fluctuations in Fully Depleted Silicon-on-Insulator MOSFETs

“…If the two oxides are made from the same dielectric material and with the same process, then the approximation N t1 = N t2 can be considered. However, the high-k dielectric used in the front gate to reduce the leakage current degrades the interface quality compared to buried thermal oxide, resulting in N t1 values typically one decade higher than N t2 [17]. Nevertheless, from (23), it becomes clear that the defining factor for the coupling effect between the two noise sources is the product ( 2 , revealing that the contribution of the back interface to the total drain current noise is not just depending on the back/front trap density ratio, but also on the back/front transconductance and oxide thickness ratios.…”

“…where α 0 = 10 5 Vs/C approximately in ultra-thin body SOI devices [17] and λ c =1.2 nm. As obtained by the numerical simulations shown in Figure 7 (after [17]) for a constant drain current, the strong dependence of the charge centroid / interface distance on the back-bias voltage V G2 results in a significant increase of the RCS coefficient  sc -through (26)-for negative values of V G2 . This occurs because as the bottom interface goes towards accumulation region, for the same total charge, the centroid moves much closer to the front interface.…”

“…Due to this coupling, it is difficult to predict precisely the contribution of each interface to the measured noise. Moreover, application of a positive or negative bias voltage to the buried oxide can possibly lead to the appearance of either Lorentzian-type noise [10], [15], [16], or a significant increase of the flicker noise level [11], [17]. Thus, the analytical study of the noise sources and their dependence on the bias conditions is crucial for both device characterization and noise modeling.…”

Optimization and scaling of an SOI TFET with back gate control

“…The effect of band-to-band generation rate on back gate voltage and body layer thickness is also presented. The control of back gate voltage on MOSFET is already established in literature [10].…”