The sharpness of tips used in scanning tunneling microscopy (STM) is one factor which affects the resolution of the STM image. In this paper, we report on a direct-current (dc) drop-off electrochemical etching procedure used to sharpen tips for STM. The shape of the tip is dependent on the meniscus which surrounds the wire at the air–electrolyte interface. The sharpness of the tip is related to the tensile strength of the wire and how quickly the electrochemical reaction can be stopped once the wire breaks. We have found that the cutoff time of the etch circuit has a significant effect on the radius of curvature and cone angle of the etched tip; i.e., the faster the cutoff time, the sharper the tip. We have constructed an etching circuit with a minimum cut-off time of 500 ns which uses two fast metal–oxide semiconductor field effect transistors (MOSFET) and a high-speed comparator. The radius of curvature of the tips can be varied from approximately 20 to greater than 300 nm by increasing the cutoff time of the circuit.

With a scanning tunneling microscope (STM) operating in vacuum, we have studied the lithographic patterning of self-assembling organosilane monolayer resist films. Where the organic group is benzyl chloride, the resist layer can be patterned with electrons down to 4 eV in energy. The patterned films have been used as templates for the electroless plating of thin Ni films. Linewidths down to ∼20 nm have been observed in scanning electron micrographs of the plated films. Still smaller features are observed in STM images of the exposed organosilane films.

In this the 50th anniversary year of the AVS and the AVS Symposium, this article is offered as one in a series of topical review articles to celebrate the role of this community to the progress in nanofabrication technology. The emphasis of the article is on the principles and limits of the various pattern formation techniques which have emerged as important tools in the research of nanoscale devices and structures. Topics such as e-beam lithography, proximal probes, imprint lithography, self assembly, and directed assembly are all discussed.

The surface morphology of a surface-bound colloidal Pd(II) catalyst and its effect on the particle size of an electroless Ni deposit is examined. The deposited catalyst is found to have a broad distribution of particle sizes with the largest particles reaching approximately 50 nm in diameter. Catalyst surface coverages as low as 20% are found to be sufficient to initiate complete and homogenous metallization. The distribution of particle sizes for the electroless metal deposit, found to be a function of plating time, is broad with the maximum Ni particle size exceeding 120 nm. Results indicate controlling the size of the bound catalyst is the principal determining factor in controlling the particle size of the electroless deposit. Modification of the surface by depleting the concentration of surface functional groups capable of binding catalyst is used to shift the size distribution of bound catalyst to smaller values. A resulting three-to fourfold reduction in the particle size of the electroless deposit is demonstrated.

Articles you may be interested inSelf-aligned fabrication of 10 nm wide asymmetric trenches for Si/SiGe heterojunction tunneling field effect transistors using nanoimprint lithography, shadow evaporation, and etching J.

We have fabricated a nanometer-scale transistor that operates by using a gate field to modulate the transmission of electrons through a lateral metal/oxide tunnel barrier. Our initial devices have a 30-nm-wide lateral Nb/NbOx tunnel junction on top of a planar Al2O3/Al buried gate. We observe effective modulation of the source–drain current with gate bias at room temperature with negligible gate leakage current. We identify the materials issues that currently limit the device performance, and we offer direction for future device improvements.

Parallel or Sequential?It is yet unclear what type of new devices, if any, will replace the metaloxide field effect transistor in the sub-0.1-ju.m domain. Since in any case, the development of quantum-effect devices requires smaller and smaller dimensions for operation above temperatures of a few milliKelvin, we can safely assume that high-resolution patterning steps will always be required to manufacture the devices themselves. Alternative approaches (such as the use of self-assembling systems) have not yet reached a convincing level of demonstration. Furthermore we can assume that the complexity of the circuits will continue to increase because this is the true driving force of miniaturization. In order to process large amounts of information in a short amount of time, the processing circuit must be correspondingly complex. Hence the future quantum devices will continue the development pattern of modern electronics, leading to the fabrication of large chips with very small devices-that is, exceedingly large processing power. The apparent insatiability of our appetites for more memory and processing makes this prediction an almost certain evolution of the current technology.

The scanning tunneling microscope (STM), operated in vacuum in the field emission mode, has been used in lithographic studies of the resist SAL-601 from Shipley. Patterns have been written by raising the tip-sample voltage above-12 V while operating the STM in the constant current mode. Resist films, 50 nm thick, have been patterned and the pattern transferred into the GaAs substrate by reactive ion etching. The variation of feature size with applied dose and tip-sample bias voltage has been studied. Comparisons have been made to lithography with a 10 nm, SO kV electron e-beam in a JEOL JBX-SDII in the same resist thickness films. In all cases the resist films were processed in the standard fashion before and after exposure. The STM can write smaller minimum features sizes and has a greater process latitude. Proximity effects are absent due to the reduced scattering range of the low energy primary electrons. However, the writing speed is slower, being limited by the response of the piezoelectric scanner. Advances have been made recently in the construction of fast STMs which scan at video rates making the STM comparable in speed to the JEOL for nanolithography. The development of ultralow voltage e-beam lithography based on STM technology is discussed.