This paper reports the development of a thermal chemical vapor deposition process for pure cobalt from the source precursor cobalt tricarbonyl nitrosyl for incorporation in integrated circuit silicide applications. Studies were carried out to examine the underlying mechanisms that control Co nucleation and growth kinetics, including the effects of key process parameters on film purity, texture, morphology, and electrical properties. For this purpose, systematic variations were implemented for substrate temperature, precursor flow, hydrogen reactant flow, and deposition time (thickness). Resulting films were analyzed by Rutherford backscattering spectrometry, X-ray photoelectron spectroscopy, X-ray diffraction, fourpoint resistivity probe, scanning electron microscopy, and atomic force microscopy. These investigations identified an optimized process window for the growth of pure Co with resistivity of 9 + 2 µΩ cm, smooth surface morphology, and root-mean-square surface roughness at or below 10% of film thickness.
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ERRATAErratum: ''Low temperature metalorganic chemical vapor deposition of tungsten nitride as diffusion barrier for copper metallization'' †J.
As industry trends drive increased integration and speed, Cuilow-k structures are the desired choice for advanced IC circuits. A simulation methodology has been developed to study the flip-chip packaging effect on the Cullow-k structures. Multi-level submodeling techniques have heen used to bridge the scale difference between the flip-chip packages and the metalidielectric stacks. Interface fracture mechanics-based approach is used to determine the crack driving force at each interface. The impact of the die-attach process on interconnect reliability has been evaluated.To achieve smaller feature size and higher speed in future chips, we can replace Si02 with low-k dielectric material in all via and trench layers, or increase the number of metal layers. This paper evaluates the effect of placing low-k as last metal dielectric and low-k at all via and trench layers, as well as the effect of eight-layer metal/dielectric stack compared with the four-layer metal stack.The future flip-chip Cuilow-k packages are facing higher possibilities of adhesive or cohesive failure near the low-k interface. This paper provided a quantitative evaluation of the increased risk, thus providing guidelines to the next level of low-k flipchip packages.
This paper reports the development of a methodology for the growth of epitaxial CoSi2 that uses Co films deposited by low temperature (390°C) chemical vapor deposition (CVD) from cobalt tricarbonyl nitrosyl [Co(CO)3NO] as source precursor. This CVD process exploits the reaction kinetics associated with the adsorption and decomposition of CoCO)3NO on Si surfaces to ensure the in situ, sequential growth of an ultrathin interfacial oxide layer followed by a Co thin film in a single deposition step. It is demonstrated that this interlayer, consisting of a Si-O or a Co-Si-O phase, inhibits silicidation for uncapped CVD Co regardless of annealing times and temperatures. Instead, Co agglomeration is observed, with the degree of agglomeration being proportional to the annealing temperature. The agglomeration is due to a reduction in the overall energy of the system through decrease of the Co/substrate interfacial area. Alternatively, for Ti/TiN capped CVD Co samples, the interfacial layer appears to play a role similar to that observed for similar layers in interlayer mediated epitaxy (IME). This assessment is supported by the observation of epitaxial CoSi2 for capped CVD Co samples after a single-step anneal at 725°C for 30 s. In contrast, Ti/TiN capped PVD Co samples annealed under identical processing conditions exhibited a polycrystalline CoSi2 phase with a strong (200) texture. As such, the methodology presented herein represents a modified IME technique for the growth of high quality, epitaxial CoSi2 films for applications in emerging microelectronics device technologies.
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