Analysis of flip-chip packaging challenges on copper low-k interconnects

Abstract

As industry trends drive increased integration and speed, Cuilow-k structures are the desired choice for advanced IC circuits. A simulation methodology has been developed to study the flip-chip packaging effect on the Cullow-k structures. Multi-level submodeling techniques have heen used to bridge the scale difference between the flip-chip packages and the metalidielectric stacks. Interface fracture mechanics-based approach is used to determine the crack driving force at each interface. The impact of the die-attach process on interconnect reliability has been evaluated.To achieve smaller feature size and higher speed in future chips, we can replace Si02 with low-k dielectric material in all via and trench layers, or increase the number of metal layers. This paper evaluates the effect of placing low-k as last metal dielectric and low-k at all via and trench layers, as well as the effect of eight-layer metal/dielectric stack compared with the four-layer metal stack.The future flip-chip Cuilow-k packages are facing higher possibilities of adhesive or cohesive failure near the low-k interface. This paper provided a quantitative evaluation of the increased risk, thus providing guidelines to the next level of low-k flipchip packages.

Integration of GMR-based spin torque oscillators and CMOS circuitry

“…2(b). This interconnection is produced by an extra build-up process step that adds bumps to all the pads on the entire wafer [21]. To integrate STOs with ICs by using flip-chip, STOs are placed on coplanar waveguides so that they can be connected to the bumps on ICs.…”

Facing the challenge of designing for Cu/low-k reliability

“…Eventually, high-filler compounds with CTE values better matching to silicon gave sufficient results. For flip-chip packages, a solution was found in changing the metal layout in the IC layers [22,23]. For instance, the placement of active circuitry in the region beneath bondpads represents an effective method for not sacrificing either assembly or package reliability.…”

“…FE techniques are widely used to predict the deformations and stresses and their evolution during IC processes, packaging manufacturing processes, and/or product testing [4,5,8,[17][18][19][20][21][22][23][24][25][26]. Modelling techniques such as contact elements, global-local, sub-structuring, element birth and death, fracture mechanics and material models such as visco-elasticity, plasticity and creep are rapidly developed to predict the stress and strain state in the electronic Fig.…”

Investigation of Mechanical Reliability of Cu/low-k Multi-layer Interconnects in Flip Chip Packages

“…Mercado et al found that the crack driving force at the critical interface increases with increasing number of interconnect layers [3]. They showed that the crack driving force for low-k structures is higher than that for SiO 2 interconnects.…”