Impact of flip-chip packaging on copper/low-k structures

Predictions and measurements of interfacial adhesion among encapsulated thin films of flexible devices

“…Interfacial cracking is significantly affected by different factors, such as the adhesion property of the bi-material and the mismatch level between their modulus. Consequently, the crack propagates with a slight distance and extends parallel to the bonding interface [23]. The FEA simulation results based on the interfacial fracture mechanics and detailed analysis are presented in the succeeding section to validate the fracture behavior during the adhesion measurement of 4-PBT.…”

Facing the challenge of designing for Cu/low-k reliability

“…Eventually, high-filler compounds with CTE values better matching to silicon gave sufficient results. For flip-chip packages, a solution was found in changing the metal layout in the IC layers [22,23]. For instance, the placement of active circuitry in the region beneath bondpads represents an effective method for not sacrificing either assembly or package reliability.…”

“…FE techniques are widely used to predict the deformations and stresses and their evolution during IC processes, packaging manufacturing processes, and/or product testing [4,5,8,[17][18][19][20][21][22][23][24][25][26]. Modelling techniques such as contact elements, global-local, sub-structuring, element birth and death, fracture mechanics and material models such as visco-elasticity, plasticity and creep are rapidly developed to predict the stress and strain state in the electronic Fig.…”

Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow

“…These are TSV etching and filling, wafer/die thinning, wafer bumping, high-temperature solder reflow, chip stacking, etc. 3,5 Hence, it is important to have a capability to accurately assess the stress generated during 3-D IC stacking.…”