Series-parallel association of transistors for the reduction of random offset in non-unity gain current mirrors

Fiorelli, Rafaella; Arnaud, Alfredo; Galup-Montoro, Carlos

doi:10.1109/iscas.2004.1328336

Cited by 11 publications

(2 citation statements)

References 13 publications

(22 reference statements)

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“…This can be viewed as the ULV implementation of the OTA reported in [20], previously proposed by the authors to enhance the bandwidth efficiency. The current gains obtained by means of conventional current mirrors in [20] are not feasible in ULV conditions and have to be implemented by means of other solutions such as the one presented in [48]. In the ULV architeture proposed in this paper, the current gains are implemented by using a different approach which is based on the body-to-gate (B2G) interfaces as will be detailed in the following.…”

Section: Introductionmentioning

confidence: 99%

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

Centurelli

Sala

Monsurrò

et al. 2022

JLPEA

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In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.

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Section: Introductionmentioning

confidence: 99%

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

Centurelli

Sala

Monsurrò

et al. 2022

JLPEA

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“…In general, an analog design is composed by transistors of different widths and lengths, which makes it less amenable to design-for-yield techniques, and requires more layout generation effort to minimize variations and improve matching [4]. Substituting each conventional single transistor in the analog circuit by an equivalent association of same size unit transistors can be a good option, minimizing and averaging variations due to layout regularity [3] [5]. Total or partial layout regularity can be achieved using the methodology of splitting a large single transistor into a series-parallel association of unit transistors.…”

Section: Introductionmentioning

confidence: 99%

T-shaped association of transistors

Girardi

Cortes

Conrad

et al. 2005

Proceedings of the 18th Annual Symposium on Integrated Circuits and System Design - SBCCI '05

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This work presents an analysis of a new type of composite transistor specially suited for the design of analog integrated circuits: the T-shape association of transistors. This association is composed by non-equal size unit transistors arranged in a series-parallel array with common gate, which can substitute the conventional rectangular transistors with advantages in some aspects, such as better high-frequency performance, lower output conductance and layout regularity. Dedicated tools that automatically translate the single transistors into equivalent associations without degradation in the overall circuit specifications guarantee the compatibility with the conventional analog design methodology. Some properties and applications are discussed in this paper. Experimental and simulated characteristics are shown in order to verify the behavior of the association.

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Performance and simulation accuracy evaluation of analog circuits with enclosed layout transistors

Cardoso

Balen

2017

Analog Integr Circ Sig Process

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Series-parallel association of transistors for the reduction of random offset in non-unity gain current mirrors

Cited by 11 publications

References 13 publications

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

T-shaped association of transistors

Performance and simulation accuracy evaluation of analog circuits with enclosed layout transistors

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