A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

Abstract

In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.

Bridging the Gap between Design and Simulation of Low-Voltage CMOS Circuits

“…The transconductance-to-current ratios, in terms of inversion level, are given by using expressions (10)- (12) in which I D,sat stands for the approximation of the drain current in the saturation region, where i r << i f [13].…”

“…In the fast expanding ultra-low-voltage domain [6], some short-channel effects, such as velocity saturation, are not relevant; thus, a simplified MOSFET model can be satisfactory for circuit design. Targeting the increasing number of ultra-low-voltage designs [7][8][9][10][11][12], this work proposes a four-parameter model (4PM) based on the all-region advanced compact MOSFET model (ACM) [13].…”

A body‐driven rail‐to‐rail 0.3 V operational transconductance amplifier exploiting current gain stages

“…Each of these stages performs differential to single-ended conversion exploiting a current mirror connection (M n 1 -M n 2 and M p 1 -M p 2 , respectively): The use of regular current mirrors, as opposed to body-driven current mirrors, allows minimizing the current gain error, improving the common-mode rejection ratio (CMRR). 45 As discussed before, each stage provides current gain through ratioed current mirrors (M n 1 -M n 2 and M p 5 -M p 6 for the up section, M p 1 -M p 2 and M n 5 -M n 6 for the down one), and the currents are recombined in two push-pull output stages that drive the second stage.…”

“…As an alternative approach, body-driven and gate-biased OTAs are much more suitable for such scanty supply voltages, and as a consequence, this has raised an ever-increasing interest in body-driven architectures. [31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46] Indeed, gate-bias configurations allow controlling the operating point over the whole dynamic range and are thus more robust when supply voltage or temperature variations are considered. However, body-driven techniques present some drawbacks with respect to gate-driven architectures, such as higher noise, lower bandwidth, and worse slew-rate behavior.…”

A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations

“…Most ULV OTAs in the literature exploit body driving (the input signal is applied to the body terminal) [9], [13]- [21], complementary n-type and p-type pseudodifferential transconductors [22] or floating-gate and quasifloating-gate solutions [23]. CMRR is improved by the use of common mode feedback (CMFB) loops, common mode feedforward (CMFF) [9], [24], by optimizing the topology of differential-to-single-ended converter (D2S) stages [21] or by optimizing the OTA architecture [20]; gain can be improved by exploiting positive feedback [15], [18] or by using additional gain stages [14], [16], [17], [19].…”