Selective wordline voltage boosting for caches to manage yield under process variations

Abstract

One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this work, we present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. We then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations. We show that our approach can eliminate over 80% of the yield losses under medium level of variations, while incurring less than 1% per-access energy overhead on average and less than 4.5% area overhead.

An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

“…In the meantime, many studies have been focusing on mitigating process variation in 2D microprocessors [14][15] [16][17] [10][8] [18]. On the other hand, in 3D microprocessors, process variation is much more severe than in 2D microprocessors.…”

“…Though the device parameters in the L2 cache have a spatial correlation, the SRAM failures are incurred in a random fashion, rather than in a spatially-correlated fashion [14] [10]. Figure 10 presents normalized energy consumption of the L2 cache based on three different cache linelevel fault rates: 30%, 40%, and 50%.…”

“…Most studies for mitigating process variation are focused on 2D chips [15] [17][10] [14] rather than 3D chips. There have been a few studies that are aimed at 3D microprocessors.…”

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

“…This technique characterizes the spread of spatial variability using empirical results that may/may not correlate with on-chip measurements. In [26], latency of failing wordlines is improved by boosting wordline voltage. Failing wordlines are tested during manufacturing and using an EEPROM, failure information is stored.…”

Exploiting narrow-width values for process variation-tolerant 3-D microprocessors

“…For example, caches, register files, and buffer structures (e.g., issue queues) are known to be most vulnerable. In typical 2D microprocessors, among these SRAMbased components, L1 caches are known to be most vulnerable to process variation [21]. On the other hand, in 3D microprocessors, last-level caches (LLC: L2 or L3 caches) are known to be the most vulnerable components.…”