On-chip network is becoming critical to the scalability of future many-core architectures. Recently, nanophotonics has been proposed for on-chip networks because of its low latency and high bandwidth. However, nanophotonics has relatively high static power consumption, which can lead to inefficient architectures. In this work, we propose FlexiShare -a nanophotonic crossbar architecture that minimizes static power consumption by fully sharing a reduced number of channels across the network. To enable efficient global sharing, we decouple the allocation of the channels and the buffers, and introduce novel photonic token-stream mechanism for channel arbitration and credit distribution.The flexibility of FlexiShare introduces additional router complexity and electrical power consumption. However, with the reduced number of optical channels, the overall power consumption is reduced without loss in performance. Our evaluation shows that the proposed token-stream arbitration applied to a conventional crossbar design improves network throughput by 5.5× under permutation traffic. In addition, FlexiShare achieves similar performance as a token-stream arbitrated conventional crossbar using only half the amount of channels under balanced, distributed traffic. With the extracted trace traffic from MineBench and SPLASH-2, FlexiShare can further reduce the amount of channels by up to 87.5%, while still providing better performance -resulting in up to 72% reduction in power consumption compared to the best alternative.

No abstract

No abstract

Abdominal pain and abnormal bowel habits represent major symptoms for irritable bowel syndrome (IBS) patients that are not adequately managed. Although the etiology of IBS is not completely understood, many of the functions of the gastrointestinal (GI) tract are regulated by the enteric nervous system (ENS). Inflammation or stress-induced expression of growth factors or cytokines may lead to hyperinnervation of visceral afferent neurons in GI tract and contribute to the pathophysiology of IBS. Rearranged during transfection (RET) is a neuronal growth factor receptor tyrosine kinase critical for the development of the ENS as exemplified by Hirschsprung patients who carry RET loss-of-function mutations and lack normal colonic innervation leading to colonic obstruction. Similarly, RET signaling in the adult ENS maintains neuronal function by contributing to synaptic formation, signal transmission, and neuronal plasticity. Inhibition of RET in the ENS represents a novel therapeutic strategy for the normalization of neuronal function and the symptoms of IBS patients. Herein, we describe our screening effort and subsequent structure-activity relationships (SARs) in optimizing potency, selectivity, and mutagenicity of the series, which led to the discovery of a first-in-class, gut-restricted RET kinase inhibitor, 2-(4-(4-ethoxy-6-oxo-1,6-dihydropyridin-3-yl)-2-fluorophenyl)--(5-(1,1,1-trifluoro-2-methylpropan-2-yl)isoxazol-3-yl)acetamide (, GSK3179106), as a clinical candidate for the treatment of IBS. GSK3179106 is a potent, selective, and gut-restricted pyridone hinge binder small molecule RET kinase inhibitor with a RET IC of 0.3 nM and is efficacious .

No abstract

Sharing on-chip network resources efficiently is critical in the design of a cost-efficient network on-chip (NoC). Concentration has been proposed for on-chip networks but the trade-off in concentration implementation and performance has not been well understood. In this paper, we describe cost-efficient implementations of concentration and show how external concentration provides a significant reduction in complexity (47% and 36% reduction in area and energy, respectively) compared to previous assumed integrated (high-radix) concentration while degrading overall performance by only 10%. Hybrid implementations of concentration is also presented which provide additional tradeoff between complexity and performance. To further reduce the cost of NoC, we describe how channel slicing can be used together with concentration. We propose virtual concentration which further reduces the complexity -saving area and energy by 69% and 32% compared to baseline mesh and 88% and 35% over baseline concentrated mesh.

Variability in device characteristics, i.e., parametric variations, is an important problem for shrinking process technologies. They manifest themselves as variations in performance, power consumption, and reduction in reliability in the manufactured chips as well as low yield levels. Their implications on performance and yield are particularly profound on 3D architectures: a defect on even a single layer can render the entire stack useless. In this paper, we show that instead of causing increased yield losses, we can actually exploit 3D technology to reduce yield losses by intelligently devising the architectures. We take advantage of the layer-to-layer variations to reduce yield losses by splitting critical components among multiple layers. Our results indicate that our proposed method achieves a 30.6% lower yield loss rate compared to the same pipeline implemented on a 2D architecture.

No abstract