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Variability in device characteristics, i.e., parametric variations, is an important problem for shrinking process technologies. They manifest themselves as variations in performance, power consumption, and reduction in reliability in the manufactured chips as well as low yield levels. Their implications on performance and yield are particularly profound on 3D architectures: a defect on even a single layer can render the entire stack useless. In this paper, we show that instead of causing increased yield losses, we can actually exploit 3D technology to reduce yield losses by intelligently devising the architectures. We take advantage of the layer-to-layer variations to reduce yield losses by splitting critical components among multiple layers. Our results indicate that our proposed method achieves a 30.6% lower yield loss rate compared to the same pipeline implemented on a 2D architecture.

One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this work, we present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. We then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations. We show that our approach can eliminate over 80% of the yield losses under medium level of variations, while incurring less than 1% per-access energy overhead on average and less than 4.5% area overhead.

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Variability is one of the important issues in nanoscale processors. Due to increasing importance of interconnect structures in submicron technologies, the physical location and phenomena such as coupling have an increasing impact on the latency of operations. Therefore, traditional view of rigid access latencies to components will result in suboptimal architectures. In this paper, we devise a cache architecture with variable access latency. Particularly, we a) develop a non-uniform access level 1 datacache, b) study the impact of coupling and physical location on level 1 data cache access latencies, and c) develop and study an architecture where the variable latency cache can be accessed while the rest of the pipeline remains synchronous. To find the access latency with different input address transitions and environmental conditions, we first build a SPICE model at a 45nm technology for a cache similar to that of the level 1 data cache of the Intel Prescott architecture. Motivated by the large difference between the worst and best case latencies and the shape of the distribution curve, we change the cache architecture to allow variable latency accesses. Since the latency of the cache is not known at the time of instruction scheduling, we also modify the functional units with the addition of special queues that will temporarily store the dependent instructions and allow the data to be forwarded from the cache to the functional units correctly. Simulations based on SPEC2000 benchmarks show that our variable access latency cache structure can reduce the execution time by as much as 19.4% and 10.7% on average compared to a conventional cache architecture.

Abstract

Cloud is the system that maintains common information sharing among the information devices. It is known that there are always risks and that hundred per cent safety is not available in the environments of information technology. Service providers that operate in accounting sector and utilize the cloud technology are responsible for keeping and preserving the digital financial data that are vitally important for the companies. Service providers need to take all the necessary technical measures, so that the digital data are not damaged, lost and possessed by the malicious third parties. The establishments that provide service for accounting systems by utilizing the cloud computing opportunities in accounting field need to consider the general and countryspecific risks of cloud computing technology. Therefore, they need to build the necessary technical infrastructure and models in order to run the system flawlessly and to preserve the digital data of the establishments in a secure environment.

Recycling of nutrient‐rich organic wastes in agricultural or horticultural practices is one of the most sustainable methods for both waste management and soil amendment. In this regard, high nutrient‐demanding horticultural crops can utilize a recycling route of organic wastes abattoir waste after appropriate processing for plantation. In this study, sustainable recycling of poultry abattoir sludge (PAS) was explored for the cultivation of walnut (Juglans regia L.) in low‐fertility soil, considering agronomic, economic factors, and associated environmental impacts based on the energy use. Tree growth rates and leaf nutrient contents were evaluated in plants fertilized with the conventional method as control treatment and four different doses of PAS amendments. Results of economical assessment and cost analysis indicated that the PAS dose of 400 g N tree−1 had the lowest cost and was determined as the most appropriate nutrient proportion for fertilization practices on walnut plantation in marginal land, and the use of PAS for fertilization resulted in about 65.4% savings in terms of present value evaluation based on three cultivation years. Findings of the present study clearly concluded that agronomic, economic, and ecological advantages of waste utilization, such as PAS application on walnut plantation, could significantly contribute to establish sustainable management and crop production alternatives for eco‐efficient cultivation systems. © 2019 American Institute of Chemical Engineers Environ Prog, 38: e13225, 2019