2009 3rd ACM/IEEE International Symposium on Networks-on-Chip 2009
DOI: 10.1109/nocs.2009.5071477
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Exploring concentration and channel slicing in on-chip network router

Abstract: Sharing on-chip network resources efficiently is critical in the design of a cost-efficient network on-chip (NoC). Concentration has been proposed for on-chip networks but the trade-off in concentration implementation and performance has not been well understood. In this paper, we describe cost-efficient implementations of concentration and show how external concentration provides a significant reduction in complexity (47% and 36% reduction in area and energy, respectively) compared to previous assumed integra… Show more

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Cited by 50 publications
(30 citation statements)
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“…A local strategy (LOCAL), NoP, RCA-1D 3 and DBSS are implemented for different size meshes. Finally, we extend the evaluation to concentrated meshes [2], [32].…”
Section: Discussionmentioning
confidence: 99%
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“…A local strategy (LOCAL), NoP, RCA-1D 3 and DBSS are implemented for different size meshes. Finally, we extend the evaluation to concentrated meshes [2], [32].…”
Section: Discussionmentioning
confidence: 99%
“…Here, we extend the analysis to the concentrated mesh (CMesh) topology [2], [32]. As a case study, we use radix-4 CMeshes [2], [32]; four cores are concentrated around one router, with two cores in each dimension, as shown in Fig.…”
Section: Concentrated Mesh Evaluationmentioning
confidence: 99%
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“…They also use integrated concentration [24] of 4 cores per network gateway, for a total core count of 256.…”
Section: A On-chip Network Architecturesmentioning
confidence: 99%
“…External concentration [24] is used because of the relative difficulty of designing high-radix photonic switches, and to reduce the number of modulator/detector banks. Designs of 4×4 photonic switches in the context of networks have been explored in [5], but because a mesh router requires 5 ports (4 directions + processor core), we must reconsider the design of the photonic switches to minimize power and insertion loss.…”
Section: A On-chip Network Architecturesmentioning
confidence: 99%