An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

Abstract

As process technologies evolves, tackling process variation problems is becoming more challenging in 3D (i.e., diestacked) microprocessors. Process variation adversely affects performance, power, and reliability of the 3D microprocessors, which in turn results in yield losses. In particular, last-level caches (LLCs: L2 or L3 caches) are known as the most vulnerable component to process variation in 3D microprocessors. In this paper, we propose a novel cache architecture that exploits narrowwidth values for yield improvement of LLCs (in this paper, L2 caches) in 3D microprocessors. Our proposed architecture disables faulty cache subparts and turns on only the portions that store meaningful data in the cache arrays, which results in high energy-efficiency as well as high cache yield. In an energy-/performance-efficient manner, our proposed architecture significantly recovers not only SRAM cell failure-induced yield losses but also leakage-induced yield losses.

Near-Threshold L1 Data Cache for Yield Management Under Process Variations

“…WBD disables the faulty cache lines (blocks). Please note that this technique is widely used, simple, practical, and also introduced in [8] (similar to Intel Pellston Technology), [9], and [10] (introduced as a naïve way reduction scheme). Though this scheme could always lead to 100% cache yield by employing the adaptive cache bypassing (i.e., bypasses cache if there is no non-faulty blocks in a cache set), the effective cache capacity would be significantly reduced, eventually causing performance losses.…”

“…For energy comparison, we further classify the WBD technique into the cases where the Gated-Vdd [23] is applied (WBD w/ Gated-Vdd) and not applied (WBD w/o Gated-Vdd). In the case of WBD w/ GVdd, the disabled cache block is powered off to reduce leakage power consumption (as in [9] and [10]) while the WBD w/o Gated-Vdd (WBD w/o GVdd) does not apply the Gated-Vdd. Compared to the ideal case (i.e., baseline), VL_base and VL_mig show energy overheads of only 7.5% and 7.3%, respectively.…”

“…Moreover, compared to a frequency (speed) binning technique [7] that is widely used for yield improvement, our proposed cache architecture improves not only yield but also performance and energy efficiency. In addition, as compared to disabling the faulty cache blocks (WBD) [8] (similar to Intel Pellston Technology) [9], [10] (introduced as a naïve way reduction scheme), our technique leads to much better performance with comparable yield even under severe process variations. Considering that the yield significantly affects the profitability of the chip manufacturing companies, our work can be a promising alternative to future near-threshold processor design for manufacturability.…”

Router-integrated Cache Hierarchy Design for Highly Parallel Computing in Efficient CMP Systems

“…Some researchers try to reduce energy consumption by applying the dynamic voltage and frequency scaling technique to manage the shared cache network [20], or proposing novel tree-based directory to bridge plenty of shared cache portions in 3D network [21]. The research in [22] proposed a novel narrow-width-value based stacked 3D cache architecture for both energy saving and yield improvement. The research in [23] tried to use thermal information in the shared cache to adaptively balance runtime status.…”

Filter router: An enhanced router design for efficient stacked shared cache network

“…Although many recent researches discover that stacked architectures are greatly adapted in area saving, network interconnection and layout optimization [8,21], however, those architectures are limited in their ability to match locality distributions among applications, and to manage highly shared data efficiently as each application contains different behaviors on runtime system latency, performance and energy debit [29]. Moreover, situations are more critical in shared last level cache, because the shared cache should serve too many threads for many data sharing, resulting in serious efficiency and coherence problems [15,17,26]. For better management of the shared cache, partitioned cache methods [1,7,22] are proposed, which can allocate cache parts into several groups corresponding to each thread.…”