Exploiting narrow-width values for process variation-tolerant 3-D microprocessors

Kong, Joonho; Chung, Sung Woo

doi:10.1145/2228360.2228581

Cited by 11 publications

(17 citation statements)

References 30 publications

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“…• We propose a novel leakage-optimized PV-aware LLC architecture with a small area overhead (∼10%), which enables yield improvement and cache energy saving with a small performance overhead; • Our new architecture enables near-optimal leakage energy savings in the LLC by considering the data type information and turning on cache portions that store meaningful data; • Our design-time technique for leakage-induced yield loss recovery further improves microprocessor LLC yield by up to 10% compared to our previously proposed architecture [3] and shows considerable elimination of the leakage-induced yield losses; • We provide energy and performance evaluation results with various fault rates. The results in the case of the high fault rates enable a futuristic projection for our cache architecture (i.e., in the case of using more advanced process technologies).…”

Section: Introductionmentioning

confidence: 91%

“…First, we describe our PV-aware data storing mechanism [3] in Section 4.1. We then explain our leakage optimization technique which can be built on the top of our PV-aware 3D L2 cache architecture [3].…”

Section: Our Energy-efficient 3d L2 Cache Architecture For Pv-tolerancementioning

confidence: 99%

“…We then explain our leakage optimization technique which can be built on the top of our PV-aware 3D L2 cache architecture [3].…”

Section: Our Energy-efficient 3d L2 Cache Architecture For Pv-tolerancementioning

confidence: 99%

“…By exploiting an architectural insight referred to as narrow-width values, our novel cache architecture saves many faulty cache lines under severe process variation, which results in significant yield improvement in a highly energyefficient manner with only a small performance loss and area overhead. By referring to the data values actually stored in the LLC arrays, our architecture applies Gated-Vdd to the '0'-stored portions in the cache arrays as well as faulty cache portions as in [3]. A significant leakage energy saving is expected, which in turn contributes to the leakage-induced yield loss reduction.…”

Section: Introductionmentioning

confidence: 99%

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An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

Kong

Koushanfar

Chung

2015

IEEE Trans. Comput.

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As process technologies evolves, tackling process variation problems is becoming more challenging in 3D (i.e., diestacked) microprocessors. Process variation adversely affects performance, power, and reliability of the 3D microprocessors, which in turn results in yield losses. In particular, last-level caches (LLCs: L2 or L3 caches) are known as the most vulnerable component to process variation in 3D microprocessors. In this paper, we propose a novel cache architecture that exploits narrowwidth values for yield improvement of LLCs (in this paper, L2 caches) in 3D microprocessors. Our proposed architecture disables faulty cache subparts and turns on only the portions that store meaningful data in the cache arrays, which results in high energy-efficiency as well as high cache yield. In an energy-/performance-efficient manner, our proposed architecture significantly recovers not only SRAM cell failure-induced yield losses but also leakage-induced yield losses.

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Section: Introductionmentioning

confidence: 91%

Section: Our Energy-efficient 3d L2 Cache Architecture For Pv-tolerancementioning

confidence: 99%

“…We then explain our leakage optimization technique which can be built on the top of our PV-aware 3D L2 cache architecture [3].…”

Section: Our Energy-efficient 3d L2 Cache Architecture For Pv-tolerancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

Kong

Koushanfar

Chung

2015

IEEE Trans. Comput.

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“…The narrow-width values in high-performance microprocessors have been well studied and exploited for performance, power, and reliability optimizations in register files and caches [11][12] [13]. In general, values with leading '0's are referred to as narrow-width values.…”

Section: Narrow Width Value For Lifetime Improvement a Narrow Wmentioning

confidence: 99%

Exploiting narrow-width values for improving non-volatile cache lifetime

Duan

Wang

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Due to the high cell density, low leakage power consumption, and less vulnerability to soft errors, non-volatile memory technologies are among the most promising alternatives for replacing the traditional DRAM and SRAM technologies used in implementing main memory and caches in the modern microprocessor. However, one of the difficulties is the limited write endurance of most non-volatile memory technologies. In this paper, we propose to exploit the narrow-width values to improve the lifetime of non-volatile last level caches. Leading zeros masking scheme is first proposed to reduce the write stress to the upper half of the narrow-width data. To balance the write variations between the upper half and the lower half of the narrow-width data, two swap schemes, the swap on write (SW) and swap on replacement (SRepl), are proposed. To further reduce the write stress to non-volatile caches, we adopt two optimization schemes, the multiple dirty bit (MDB) and read before write (RBW), to improve their lifetime. Our experimental results show that by combining all our proposed schemes, the lifetime of non-volatile caches can be improved by 245% on average.

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Near-Threshold L1 Data Cache for Yield Management Under Process Variations

Kong

Hur

2020

IEEE Access

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Near-threshold computing (NTC) has recently emerged and been considered as a strong candidate for future energy-efficient computing. However, adverse impacts from process variation such as delay and power fluctuations within die as well as across dies are much more severe than the super-threshold regime. In particular, static random access memory (SRAM)-based components (e.g., cache memories) are easily affected by process variation in NTC, resulting in large delay fluctuations. It incurs a huge loss in the maximum clock frequencies of processors, which eventually leads to huge yield losses. In this paper, we first analyze L1 data cache yield in NTC and reveal an inefficiency of frequency binning for yield improvement in NTC. We then introduce a variable latency L1 data cache for NTC to obtain a sufficient yield. By allowing the higher cache access cycles, we can improve cache yield with only a little performance overhead. Moreover, we propose an adaptive line migration technique which improves performance and energy efficiency of variable latency caches. The cache line which is expected to be frequently accessed in the near future is dynamically migrated to the fastest way in a cache set. According to our evaluation, our cache architecture greatly improves cache yield with only a little performance, energy, and area overhead.

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Exploiting narrow-width values for process variation-tolerant 3-D microprocessors

Cited by 11 publications

References 30 publications

An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

Exploiting narrow-width values for improving non-volatile cache lifetime

Near-Threshold L1 Data Cache for Yield Management Under Process Variations

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