Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

Abstract

Abstract-In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations. Front body biasing (FBB) is employed for active sub-arrays to speed up accesses while inactive sub-arrays are reverse body biased (RBB) to reduce standby leakage power. Cache subarrays are classified based on run-time leakage and latency distributions and applied bias voltage is updated to account for these changes. This ensures that under all scenarios, the cache will consume the lowest leakage power for the target access latency computed at design-time. The backbone of the hardware used for classification is the 3T1D DRAM cell embedded into conventional 6T based memory. By measuring the access and retention time of the 3T1D cell, we show that it is possible to classify cache arrays based on run-time latency/leakage measurements. The tremendous increase in energy in active mode by forward biasing (to meet latency requirements) is compensated by reverse biasing inactive arrays. Our technique reduces leakage energy consumption and access latency of the cache on average by 20% & 18% respectively when compared to other state-of-the-art proposals. Finally we show that our technique will improve parametric yield by a maximum of 38% for worst-case scenario.

Cache memory design in the FinFET era

“…Forward body biasing (FBB) decreases the threshold voltage V T H of the transistors, increasing maximum frequency and leakage, while reverse body biasing (RBB) has the opposite effect [18,19,20,21]. Tolerance to variations can be increased by utilising both RBB and FBB mutually-exclusively, and this is called Adaptive Body Biasing (ABB) [20,21,22,9].…”