Security and Vulnerability Implications of 3D ICs

Xie, Yang; Bao, Chongxi; Serafy, Caleb; Lu, Tiantao; Srivastava, Ankur; Tehranipoor, Mark

doi:10.1109/tmscs.2016.2550460

Cited by 48 publications

(13 citation statements)

References 94 publications

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“…To address and manage this challenge of verification and other security-centric challenges, the notions of "secure by design" and "design-for-trust" have been promoted for some years now for "regular" 2D chips [116], [117], [118], [119], [123], [124], [125], [126], [127], [128]. Similar studies are recently focusing on 3D chips as well [129], [130], [131], [132], [133], [134], [135], [136], [137], [138]. Note that early stud- Fig.…”

Section: Towards Trustworthy 3d Integrationmentioning

confidence: 99%

“…As indicated, this is especially attractive for 3D chips where such monitors can be implemented in trustworthy dies, separated from the potentially Trojaninfected legacy chips [127], [129], [130], [139]. Nevertheless, some Trojans may be crafted specifically for 3D integration and end up being "buried somewhere in the midst of the 3D chip"; they are harder to detect during runtime [134], and may also exploit distinct trigger mechanisms such as increased internal heating [154].…”

Section: Detection Of Hardware Trojansmentioning

confidence: 99%

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Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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Section: Towards Trustworthy 3d Integrationmentioning

confidence: 99%

Section: Detection Of Hardware Trojansmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

show abstract

“…Three-dimensional integration also introduces security vulnerability opportunities. This includes side channel analysis attack prevention, trusted computing design, and the prohibition of supply-chain-based attacks [112]. For instance, the dimensions of an integrated circuit containing many dies from different sellers are not secure because not all of the IP providers follow a similar level of die certification.…”

Section: Split Manufacturingmentioning

confidence: 99%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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Abstract:In this review article for Internet of Things (IoT) applications, important low-power design techniques for digital and mixed-signal analog-digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non-volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed. Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all-spin logic devices are highlighted. Furthermore, a novel ultra-low power design using bio-inspired neuromorphic computing and spiking neural network security are discussed.

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“…Since clock synthesis is usually performed after cell placement, layout whitespace for TSVs is limited. However, both TSVs (clock and control) occupy a large placement area and the reliability [Jung et al 2012;Xie et al 2016] and signal integrity [Liu et al 2011] requirements enforce TSVs to maintain certain keep-out areas, both of which constrain the usage of TSVs. In addition, although TSVs offer short and fast vertical connections, excessive usage of TSVs increases the manufacturing overhead and makes the system's reliability questionable, due to the degradation of TSVs over time.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Clock Tree Synthesis for 3D-ICs

Srivastava

2017

ACM Trans. Des. Autom. Electron. Syst.

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We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees' dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. In 3D-ICs, a shutdown gate is connected to a control signal unit through control TSVs, which may cause placement conflicts with existing clock TSVs in the layout due to TSV's large physical dimension. We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering and (2) clock tree embedding with simultaneous shutdown gates' insertion based on simulated annealing (SA) and a force-directed TSV placer. Experimental results indicate that (1) the K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity, and (2) the SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering control TSV's placement. Compared with previous 3D clock tree synthesis techniques, our Kmeans clustering-based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.

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Security and Vulnerability Implications of 3D ICs

Cited by 48 publications

References 94 publications

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

Low-Power Clock Tree Synthesis for 3D-ICs

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